Motorola MPC8260 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for MPC8260 Motorola
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 1006 |
| Size: | 9.93 MB |
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Document Outline
- About This Book
- PartI Overview
- Intended Audience
- Contents
- Conventions
- Acronyms and Abbreviations
- Chapter1 Overview
- Chapter2 PowerPC Processor Core
- 2.1 Overview
- 2.2 PowerPC Processor Core Features
- 2.3 Programming Model
- 2.4 Cache Implementation
- 2.5 Exception Model
- 2.6 Memory Management
- 2.7 Instruction Timing
- 2.8 Differences between the MPC8260’s Core and the PowerPC 603e Microprocessor
- Chapter3 Memory Map
- PartII Configuration and Reset
- Audience
- Contents
- Suggested Reading
- Conventions
- Acronyms and Abbreviations
- Chapter4 System Interface Unit (SIU)
- 4.1 System Configuration and Protection
- 4.2 Interrupt Controller
- 4.3 Programming Model
- 4.3.1 Interrupt Controller Registers
- 4.3.1.1 SIU Interrupt Configuration Register (SICR)
- 4.3.1.2 SIU Interrupt Priority Register (SIPRR)
- 4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)
- 4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)
- 4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)
- 4.3.1.6 SIU Interrupt Vector Register (SIVEC)
- 4.3.1.7 SIU External Interrupt Control Register (SIEXR)
- 4.3.2 System Configuration and Protection Registers
- 4.3.2.1 Bus Configuration Register (BCR)
- 4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)
- 4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)
- 4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)
- 4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)
- 4.3.2.6 SIU Module Configuration Register (SIUMCR)
- 4.3.2.7 Internal Memory Map Register (IMMR)
- 4.3.2.8 System Protection Control Register (SYPCR)
- 4.3.2.9 Software Service Register (SWSR)
- 4.3.2.10 60x Bus Transfer Error Status and Control Register1 (TESCR1)
- 4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
- 4.3.2.12 Local Bus Transfer Error Status and Control Register1 (L_TESCR1)
- 4.3.2.13 Local Bus Transfer Error Status and Control Register2 (L_TESCR2)
- 4.3.2.14 Time Counter Status and Control Register (TMCNTSC)
- 4.3.2.15 Time Counter Register (TMCNT)
- 4.3.2.16 Time Counter Alarm Register (TMCNTAL)
- 4.3.3 Periodic Interrupt Registers
- 4.3.1 Interrupt Controller Registers
- 4.4 SIU Pin Multiplexing
- Chapter5 Reset
- PartIII The Hardware Interface
- Intended Audience
- Contents
- Suggested Reading
- Conventions
- Acronyms and Abbreviations
- Chapter6 External Signals
- Chapter7 60x Signals
- 7.1 Signal Configuration
- 7.2 Signal Descriptions
- 7.2.1 Address Bus Arbitration Signals
- 7.2.2 Address Transfer Start Signal
- 7.2.3 Address Transfer Signals
- 7.2.4 Address Transfer Attribute Signals
- 7.2.5 Address Transfer Termination Signals
- 7.2.6 Data Bus Arbitration Signals
- 7.2.7 Data Transfer Signals
- 7.2.8 Data Transfer Termination Signals
- Chapter8 The 60x Bus
- 8.1 Terminology
- 8.2 Bus Configuration
- 8.3 60x Bus Protocol Overview
- 8.4 Address Tenure Operations
- 8.4.1 Address Arbitration
- 8.4.2 Address Pipelining
- 8.4.3 Address Transfer Attribute Signals
- 8.4.3.1 Transfer Type Signal (TT[0–4]) Encoding
- 8.4.3.2 Transfer Code Signals TC[0–2]
- 8.4.3.3 TBST and TSIZ[0–3] Signals and Size of Transfer
- 8.4.3.4 Burst Ordering During Data Transfers
- 8.4.3.5 Effect of Alignment on Data Transfers
- 8.4.3.6 Effect of Port Size on Data Transfers
- 8.4.3.7 60x-Compatible Bus Mode—Size Calculation
- 8.4.3.8 Extended Transfer Mode
- 8.4.4 Address Transfer Termination
- 8.4.5 Pipeline Control
- 8.5 Data Tenure Operations
- 8.6 Memory Coherency—MEI Protocol
- 8.7 Processor State Signals
- 8.8 Little-Endian Mode
- Chapter9 Clocks and Power Control
- Chapter10 Memory Controller
- 10.1 Features
- 10.2 Basic Architecture
- 10.2.1 Address and Address Space Checking
- 10.2.2 Page Hit Checking
- 10.2.3 Error Checking and Correction (ECC)
- 10.2.4 Parity Generation and Checking
- 10.2.5 Transfer Error Acknowledge (TEA) Generation
- 10.2.6 Machine Check Interrupt (MCP) Generation
- 10.2.7 Data Buffer Controls (BCTLx)
- 10.2.8 Atomic Bus Operation
- 10.2.9 Data Pipelining
- 10.2.10 External Memory Controller Support
- 10.2.11 External Address Latch Enable Signal (ALE)
- 10.2.12 ECC/Parity Byte Select (PBSE)
- 10.2.13 Partial Data Valid Indication (PSDVAL)
- 10.3 Register Descriptions
- 10.3.1 Base Registers (BRx)
- 10.3.2 Option Registers (ORx)
- 10.3.3 60x SDRAM Mode Register (PSDMR)
- 10.3.4 Local Bus SDRAM Mode Register (LSDMR)
- 10.3.5 Machine A/B/C Mode Registers (MxMR)
- 10.3.6 Memory Data Register (MDR)
- 10.3.7 Memory Address Register (MAR)
- 10.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)
- 10.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)
- 10.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
- 10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)
- 10.3.12 Memory Refresh Timer Prescaler Register (MPTPR)
- 10.3.13 60x Bus Error Status and Control Registers (TESCRx)
- 10.3.14 Local Bus Error Status and Control Registers (L_TESCRx)
- 10.4 SDRAM Machine
- 10.4.1 Supported SDRAM Configurations
- 10.4.2 SDRAM Power-On Initialization
- 10.4.3 JEDEC-Standard SDRAM Interface Commands
- 10.4.4 Page-Mode Support and Pipeline Accesses
- 10.4.5 Bank Interleaving
- 10.4.6 SDRAM Device-Specific Parameters
- 10.4.6.1 Precharge-to-Activate Interval
- 10.4.6.2 Activate to Read/Write Interval
- 10.4.6.3 Column Address to First Data Out—CAS Latency
- 10.4.6.4 Last Data Out to Precharge
- 10.4.6.5 Last Data In to Precharge—Write Recovery
- 10.4.6.6 Refresh Recovery Interval (RFRC)
- 10.4.6.7 External Address Multiplexing Signal
- 10.4.6.8 External Address and Command Buffers (BUFCMD)
- 10.4.7 SDRAM Interface Timing
- 10.4.8 SDRAM Read/Write Transactions
- 10.4.9 SDRAM Mode-Set Command Timing
- 10.4.10 SDRAM Refresh
- 10.4.11 SDRAM Refresh Timing
- 10.4.12 SDRAM Configuration Examples
- 10.4.13 SDRAM Configuration Example (Bank-Based Interleaving)
- 10.5 General-Purpose Chip-Select Machine (GPCM)
- 10.6 User-Programmable Machines (UPMs)
- 10.6.1 Requests
- 10.6.2 Programming the UPMs
- 10.6.3 Clock Timing
- 10.6.4 The RAM Array
- 10.6.5 UPM DRAM Configuration Example
- 10.6.6 Differences between MPC8xx UPM and MPC8260 UPM
- 10.7 Memory System Interface Example Using UPM
- 10.8 Handling Devices with Slow or Variable Access Times
- 10.9 External Master Support (60x-Compatible Mode)
- Chapter11 Secondary (L2) Cache Support
- Chapter12 IEEE 1149.1 Test Access Port
- PartIV Communications Processor Module
- Intended Audience
- Contents
- Suggested Reading
- Conventions
- Acronyms and Abbreviations
- Chapter13 Communications Processor Module Overview
- 13.1 Features
- 13.2 MPC8260 Serial Configurations
- 13.3 Communications Processor (CP)
- 13.4 Command Set
- 13.5 Dual-Port RAM
- 13.6 RISC Timer Tables
- 13.6.1 RISC Timer Table Parameter RAM
- 13.6.2 RISC Timer Command Register (TM_CMD)
- 13.6.3 RISC Timer Table Entries
- 13.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)
- 13.6.5 set timer Command
- 13.6.6 RISC Timer Initialization Sequence
- 13.6.7 RISC Timer Initialization Example
- 13.6.8 RISC Timer Interrupt Handling
- 13.6.9 RISC Timer Table Scan Algorithm
- 13.6.10 Using the RISC Timers to Track CP Loading
- Chapter14 Serial Interface with Time-Slot Assigner
- Chapter15 CPM Multiplexing
- Chapter16 Baud-Rate Generators (BRGs)
- Chapter17 Timers
- Chapter18 SDMA Channels and IDMA Emulation
- 18.1 SDMA Bus Arbitration and Bus Transfers
- 18.2 SDMA Registers
- 18.3 IDMA Emulation
- 18.4 IDMA Features
- 18.5 IDMA Transfers
- 18.6 IDMA Priorities
- 18.7 IDMA Interface Signals
- 18.8 IDMA Operation
- 18.9 IDMA Commands
- 18.10 IDMA Bus Exceptions
- 18.11 Programming the Parallel I/O Registers
- 18.12 IDMA Programming Examples
- Chapter19 Serial Communications Controllers (SCCs)
- 19.1 Features
- 19.2 SCC Buffer Descriptors (BDs)
- 19.3 SCC Parameter RAM
- 19.3.1 SCC Base Addresses
- 19.3.2 Function Code Registers (RFCR and TFCR)
- 19.3.3 Handling SCC Interrupts
- 19.3.4 Initializing the SCCs
- 19.3.5 Controlling SCC Timing with RTS, CTS, and CD
- 19.3.6 Digital Phase-Locked Loop (DPLL) Operation
- 19.3.7 Clock Glitch Detection
- 19.3.8 Reconfiguring the SCCs
- 19.3.9 Saving Power
- Chapter20 SCC UART Mode
- 20.1 Features
- 20.2 Normal Asynchronous Mode
- 20.3 Synchronous Mode
- 20.4 SCC UART Parameter RAM
- 20.5 Data-Handling Methods: Character- or Message- Based
- 20.6 Error and Status Reporting
- 20.7 SCC UART Commands
- 20.8 Multidrop Systems and Address Recognition
- 20.9 Receiving Control Characters
- 20.10 Hunt Mode (Receiver)
- 20.11 Inserting Control Characters into the Transmit Data Stream
- 20.12 Sending a Break (Transmitter)
- 20.13 Sending a Preamble (Transmitter)
- 20.14 Fractional Stop Bits (Transmitter)
- 20.15 Handling Errors in the SCC UART Controller
- 20.16 UART Mode Register (PSMR)
- 20.17 SCC UART Receive Buffer Descriptor (RxBD)
- 20.18 SCC UART Transmit Buffer Descriptor (TxBD)
- 20.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)
- 20.20 SCC UART Status Register (SCCS)
- 20.21 SCC UART Programming Example
- 20.22 S-Records Loader Application
- Chapter21 SCC HDLC Mode
- 21.1 SCC HDLC Features
- 21.2 SCC HDLC Channel Frame Transmission
- 21.3 SCC HDLC Channel Frame Reception
- 21.4 SCC HDLC Parameter RAM
- 21.5 Programming the SCC in HDLC Mode
- 21.6 SCC HDLC Commands
- 21.7 Handling Errors in the SCC HDLC Controller
- 21.8 HDLC Mode Register (PSMR)
- 21.9 SCC HDLC Receive Buffer Descriptor (RxBD)
- 21.10 SCC HDLC Transmit Buffer Descriptor (TxBD)
- 21.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
- 21.12 SCC HDLC Status Register (SCCS)
- 21.13 SCC HDLC Programming Examples
- 21.14 HDLC Bus Mode with Collision Detection
- Chapter22 SCC BISYNC Mode
- 22.1 Features
- 22.2 SCC BISYNC Channel Frame Transmission
- 22.3 SCC BISYNC Channel Frame Reception
- 22.4 SCC BISYNC Parameter RAM
- 22.5 SCC BISYNC Commands
- 22.6 SCC BISYNC Control Character Recognition
- 22.7 BISYNC SYNC Register (BSYNC)
- 22.8 SCC BISYNC DLE Register (BDLE)
- 22.9 Sending and Receiving the Synchronization Sequence
- 22.10 Handling Errors in the SCC BISYNC
- 22.11 BISYNC Mode Register (PSMR)
- 22.12 SCC BISYNC Receive BD (RxBD)
- 22.13 SCC BISYNC Transmit BD (TxBD)
- 22.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
- 22.15 SCC Status Registers (SCCS)
- 22.16 Programming the SCC BISYNC Controller
- 22.17 SCC BISYNC Programming Example
- Chapter23 SCC Transparent Mode
- 23.1 Features
- 23.2 SCC Transparent Channel Frame Transmission Process
- 23.3 SCC Transparent Channel Frame Reception Process
- 23.4 Achieving Synchronization in Transparent Mode
- 23.5 CRC Calculation in Transparent Mode
- 23.6 SCC Transparent Parameter RAM
- 23.7 SCC Transparent Commands
- 23.8 Handling Errors in the Transparent Controller
- 23.9 Transparent Mode and the PSMR
- 23.10 SCC Transparent Receive Buffer Descriptor (RxBD)
- 23.11 SCC Transparent Transmit Buffer Descriptor (TxBD)
- 23.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
- 23.13 SCC Status Register in Transparent Mode (SCCS)
- 23.14 SCC2 Transparent Programming Example
- Chapter24 SCC Ethernet Mode
- 24.1 Ethernet on the MPC8260
- 24.2 Features
- 24.3 Connecting the MPC8260 to Ethernet
- 24.4 SCC Ethernet Channel Frame Transmission
- 24.5 SCC Ethernet Channel Frame Reception
- 24.6 The Content-Addressable Memory (CAM) Interface
- 24.7 SCC Ethernet Parameter RAM
- 24.8 Programming the Ethernet Controller
- 24.9 SCC Ethernet Commands
- 24.10 SCC Ethernet Address Recognition
- 24.11 Hash Table Algorithm
- 24.12 Interpacket Gap Time
- 24.13 Handling Collisions
- 24.14 Internal and External Loopback
- 24.15 Full-Duplex Ethernet Support
- 24.16 Handling Errors in the Ethernet Controller
- 24.17 Ethernet Mode Register (PSMR)
- 24.18 SCC Ethernet Receive BD
- 24.19 SCC Ethernet Transmit Buffer Descriptor
- 24.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
- 24.21 SCC Ethernet Programming Example
- Chapter25 SCC AppleTalk Mode
- Chapter26 Serial Management Controllers (SMCs)
- 26.1 Features
- 26.2 Common SMC Settings and Configurations
- 26.3 SMC in UART Mode
- 26.3.1 Features
- 26.3.2 SMC UART Channel Transmission Process
- 26.3.3 SMC UART Channel Reception Process
- 26.3.4 Programming the SMC UART Controller
- 26.3.5 SMC UART Transmit and Receive Commands
- 26.3.6 Sending a Break
- 26.3.7 Sending a Preamble
- 26.3.8 Handling Errors in the SMC UART Controller
- 26.3.9 SMC UART RxBD
- 26.3.10 SMC UART TxBD
- 26.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)
- 26.3.12 SMC UART Controller Programming Example
- 26.4 SMC in Transparent Mode
- 26.4.1 Features
- 26.4.2 SMC Transparent Channel Transmission Process
- 26.4.3 SMC Transparent Channel Reception Process
- 26.4.4 Using SMSYN for Synchronization
- 26.4.5 Using the Time-Slot Assigner (TSA) for Synchronization
- 26.4.6 SMC Transparent Commands
- 26.4.7 Handling Errors in the SMC Transparent Controller
- 26.4.8 SMC Transparent RxBD
- 26.4.9 SMC Transparent TxBD
- 26.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
- 26.4.11 SMC Transparent NMSI Programming Example
- 26.5 The SMC in GCI Mode
- 26.5.1 SMC GCI Parameter RAM
- 26.5.2 Handling the GCI Monitor Channel
- 26.5.3 Handling the GCI C/I Channel
- 26.5.4 SMC GCI Commands
- 26.5.5 SMC GCI Monitor Channel RxBD
- 26.5.6 SMC GCI Monitor Channel TxBD
- 26.5.7 SMC GCI C/I Channel RxBD
- 26.5.8 SMC GCI C/I Channel TxBD
- 26.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)
- Chapter27 Multi-Channel Controllers (MCCs)
- 27.1 Features
- 27.2 MCC Data Structure Organization
- 27.3 Global MCC Parameters
- 27.4 Channel Extra Parameters
- 27.5 Super-Channel Table
- 27.6 Channel-Specific HDLC Parameters
- 27.7 Channel-Specific Transparent Parameters
- 27.8 MCC Configuration Registers (MCCFx)
- 27.9 MCC Commands
- 27.10 MCC Exceptions
- 27.11 MCC Buffer Descriptors
- 27.12 MCC Initialization and Start/Stop Sequence
- 27.13 MCC Latency and Performance
- Chapter28 Fast Communications Controllers (FCCs)
- 28.1 Overview
- 28.2 General FCC Mode Registers (GFMRx)
- 28.3 FCC Protocol-Specific Mode Registers (FPSMRx)
- 28.4 FCC Data Synchronization Registers (FDSRx)
- 28.5 FCC Transmit-on-Demand Registers (FTODRx)
- 28.6 FCC Buffer Descriptors
- 28.7 FCC Parameter RAM
- 28.8 Interrupts from the FCCs
- 28.9 FCC Initialization
- 28.10 FCC Interrupt Handling
- 28.11 FCC Timing Control
- 28.12 Disabling the FCCs On-the-Fly
- 28.13 Saving Power
- Chapter29 ATM Controller
- 29.1 Features
- 29.2 ATM Controller Overview
- 29.3 ATM Pace Control (APC) Unit
- 29.3.1 APC Modes and ATM Service Types
- 29.3.2 APC Unit Scheduling Mechanism
- 29.3.3 Determining the Scheduling Table Size
- 29.3.4 Determining the Time-Slot Scheduling Rate of a Channel
- 29.3.5 ATM Traffic Type
- 29.3.6 Determining the Priority of an ATM Channel
- 29.4 VCI/VPI Address Lookup Mechanism
- 29.5 Available Bit Rate (ABR) Flow Control
- 29.6 OAM Support
- 29.7 User-Defined Cells (UDC)
- 29.8 ATM Layer Statistics
- 29.9 ATM-to-TDM Interworking
- 29.10 ATM Memory Structure
- 29.10.1 Parameter RAM
- 29.10.2 Connection Tables (RCT, TCT, and TCTE)
- 29.10.3 OAM Performance Monitoring Tables
- 29.10.4 APC Data Structure
- 29.10.5 ATM Controller Buffer Descriptors (BDs)
- 29.10.5.1 Transmit Buffer Operations
- 29.10.5.2 Receive Buffers Operation
- 29.10.5.3 ATM Controller Buffers
- 29.10.5.4 AAL5 RxBD
- 29.10.5.5 AAL1 RxBD
- 29.10.5.6 AAL0 RxBD
- 29.10.5.7 AAL5, AAL1 User-Defined Cell—RxBD Extension
- 29.10.5.8 AAL5 TxBDs
- 29.10.5.9 AAL1 TxBDs
- 29.10.5.10 AAL0 TxBDs
- 29.10.5.11 AAL5, AAL1 User-Defined Cell—TxBD Extension
- 29.10.6 AAL1 Sequence Number (SN) Protection Table (AAL1 Only)
- 29.10.7 UNI Statistics Table
- 29.11 ATM Exceptions
- 29.12 The UTOPIA Interface
- 29.13 ATM Registers
- 29.14 ATM Transmit Command
- 29.15 SRTS Generation and Clock Recovery Using External Logic
- 29.16 Configuring the ATM Controller for Maximum CPM Performance
- Chapter30 Fast Ethernet Controller
- 30.1 Fast Ethernet on the MPC8260
- 30.2 Features
- 30.3 Connecting the MPC8260 to Fast Ethernet
- 30.4 Ethernet Channel Frame Transmission
- 30.5 Ethernet Channel Frame Reception
- 30.6 Flow Control
- 30.7 CAM Interface
- 30.8 Ethernet Parameter RAM
- 30.9 Programming Model
- 30.10 Ethernet Command Set
- 30.11 RMON Support
- 30.12 Ethernet Address Recognition
- 30.13 Hash Table Algorithm
- 30.14 Interpacket Gap Time
- 30.15 Handling Collisions
- 30.16 Internal and External Loopback
- 30.17 Ethernet Error-Handling Procedure
- 30.18 Fast Ethernet Registers
- 30.19 Ethernet RxBDs
- 30.20 Ethernet TxBDs
- Chapter31 FCC HDLC Controller
- 31.1 Key Features
- 31.2 HDLC Channel Frame Transmission Processing
- 31.3 HDLC Channel Frame Reception Processing
- 31.4 HDLC Parameter RAM
- 31.5 Programming Model
- 31.6 HDLC Mode Register (FPSMR)
- 31.7 HDLC Receive Buffer Descriptor (RxBD)
- 31.8 HDLC Transmit Buffer Descriptor (TxBD)
- 31.9 HDLC Event Register (FCCE)/Mask Register (FCCM)
- 31.10 FCC Status Register (FCCS)
- Chapter32 FCC Transparent Controller
- Chapter33 Serial Peripheral Interface (SPI)
- 33.1 Features
- 33.2 SPI Clocking and Signal Functions
- 33.3 Configuring the SPI Controller
- 33.4 Programming the SPI Registers
- 33.5 SPI Parameter RAM
- 33.6 SPI Commands
- 33.7 The SPI Buffer Descriptor (BD) Table
- 33.8 SPI Master Programming Example
- 33.9 SPI Slave Programming Example
- 33.10 Handling Interrupts in the SPI
- Chapter34 I2C Controller
- Chapter35 Parallel I/O Ports