Motorola MPC8260 - Manual (Page 578)

19-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
19.3.6 Digital Phase-Locked Loop (DPLL) Operation
Each SCC channel includes a digital phase-locked loop (DPLL) for recovering clock
information from a received data stream. For applications that provide a direct clock source
to the SCC, the DPLL can be bypassed by selecting 1x mode for GSMR_L[RDCR, TDCR].
If the DPLL is bypassed, only NRZ or NRZI encodings are available. The DPLL must not
be used when an SCC is programmed to Ethernet and is optional for other protocols.
Figure 19-13 shows the DPLL receiver block; Figure 19-14 shows the transmitter block
diagram.
Figure 19-13. DPLL Receiver Block Diagram
DPLL
HSRCLK
RXD
RINV
TSNC
EDGE
RDCR
RENC
Receiver
Carrier SNC
Decoded Data
Hunting
Noise
0
S
Recovered Clock
HSRCLK RCLK
1
1x Mode
0
S
SCCR Data
1
1x Mode
D
CLK
Q
HSRCLK
RXD
RINV
RENC ¹ NRZI