Motorola MPC8260 - Manual (Page 13)

MOTOROLA Contents xiii
CONTENTS
Paragraph
Number
Title
Page
Number
10.4.5 Bank Interleaving ........................................................................................10-36
10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA) .............................10-37
10.4.6 SDRAM Device-Specific Parameters ..........................................................10-38
10.4.6.1 Precharge-to-Activate Interval .................................................................10-38
10.4.6.2 Activate to Read/Write Interval ...............................................................10-39
10.4.6.3 Column Address to First Data OutÑCAS Latency .................................10-40
10.4.6.4 Last Data Out to Precharge ......................................................................10-40
10.4.6.5 Last Data In to PrechargeÑWrite Recovery ...........................................10-41
10.4.6.6 Refresh Recovery Interval (RFRC)..........................................................10-41
10.4.6.7 External Address Multiplexing Signal .....................................................10-41
10.4.6.8 External Address and Command Buffers (BUFCMD) ............................10-42
10.4.7 SDRAM Interface Timing............................................................................10-42
10.4.8 SDRAM Read/Write Transactions...............................................................10-46
10.4.9 SDRAM Mode-Set Command Timing ........................................................10-46
10.4.10 SDRAM Refresh ..........................................................................................10-47
10.4.11 SDRAM Refresh Timing .............................................................................10-47
10.4.12 SDRAM Configuration Examples ...............................................................10-48
10.4.12.1 SDRAM Configuration Example (Page-Based Interleaving) ..................10-48
10.4.13 SDRAM Configuration Example (Bank-Based Interleaving) .....................10-50
10.5 General-Purpose Chip-Select Machine (GPCM) .............................................10-51
10.5.1 Timing Configuration...................................................................................10-52
10.5.1.1 Chip-Select Assertion Timing..................................................................10-53
10.5.1.2 Chip-Select and Write Enable Deassertion Timing .................................10-54
10.5.1.3 Relaxed Timing........................................................................................10-55
10.5.1.4 Output Enable (OE) Timing.....................................................................10-57
10.5.1.5 Programmable Wait State Configuration .................................................10-57
10.5.1.6 Extended Hold Time on Read Accesses ..................................................10-57
10.5.2 External Access Termination .......................................................................10-60
10.5.3 Boot Chip-Select Operation .........................................................................10-61
10.5.4 Differences between MPC8xxÕs GPCM and MPC8260Õs GPCM...............10-62
10.6 User-Programmable Machines (UPMs) ...........................................................10-62
10.6.1 Requests .......................................................................................................10-64
10.6.1.1 Memory Access Requests ........................................................................10-65
10.6.1.2 UPM Refresh Timer Requests .................................................................10-65
10.6.1.3 Software RequestsÑrun Command.........................................................10-66
10.6.1.4 Exception Requests ..................................................................................10-66
10.6.2 Programming the UPMs...............................................................................10-66
10.6.3 Clock Timing ...............................................................................................10-67
10.6.4 The RAM Array ...........................................................................................10-69
10.6.4.1 RAM Words .............................................................................................10-70
10.6.4.1.1 Chip-Select Signals (CxTx) .................................................................10-74
10.6.4.1.2 Byte-Select Signals (BxTx) .................................................................10-75
10.6.4.1.3 General-Purpose Signals (GxTx, GOx) ...............................................10-76