Motorola MPC8260 - Manual (Page 379)

MOTOROLA Chapter 10. Memory Controller 10-103
Part III. The Hardware Interface
The 60x bus is pipelined. The ALE pins control the external latch that latches the address
from the 60x bus and keeps the address stable for the memory access. The memory
controller asserts ALE only on the start of new memory controller access.
Figure 10-84 shows the pipelined bus operation in 60x-compatible mode.
Figure 10-84. Pipelined Bus Operation and Memory Access in 60x-Compatible
Mode
CLKIN
ADDR + ATTR
TS
AACK
DBG
PSDVAL
D
TA
CS
WE
OE
BADDR[27–28]
ALE
MA
00 01 02 03