Motorola MPC8260 - Manual (Page 710)

26-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
26.3.9 SMC UART RxBD
Using the BDs, the CP reports information about the received data on a per-buffer basis.
Then it closes the current buffer, generates a maskable interrupt, and starts receiving data
into the next buffer after one of the following occurs:
¥ An error is received during message processing
¥ A full receive buffer is detected
¥ A programmable number of consecutive idle characters are received
Figure 26-6 shows the format of the SMC UART RxBD.
Table 26-7 describes RxBD Þelds.
Framing The SMC received a character with no stop bit. When it occurs, the channel writes the received
character to the buffer, closes the buffer, sets FR in the BD, and generates the RXB interrupt if it is
enabled. When this error occurs, parity is not checked for the character.
Break
Sequence The SMC receiver received an all-zero character with a framing error. The channel increments BRKEC,
generates a maskable BRK interrupt in SMCE, measures the length of the break sequence, and stores
this value in BRKLN. If the channel was processing a buffer when the break was received, the buffer is
closed with the BR bit in the RxBD set. The RXB interrupt is generated if it is enabled.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 E Ñ W I Ñ CM ID Ñ BR FR PR Ñ OV Ñ
Offset + 2 Data Length
Offset + 4 Rx Data Buffer Pointer
Offset + 6
Figure 26-6. SMC UART RxBD
Table 26-7. SMC UART RxBD Field Descriptions
Bit Name Description
0 E Empty.
0 The buffer is full or data reception stopped due to an error. The core can read or write any Þelds of
this RxBD. The CP does not use this BD while E is zero.
1 The buffer is empty or reception is in progress. This RxBD and its buffer are owned by the CP. Once
E is set, the core should not write any Þelds of this RxBD.
1 Ñ Reserved, should be cleared.
2 W Wrap (last BD in RxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that
RBASE points to in the table. The number of RxBDs in this table is determined only by the W bit and
overall space constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is Þlled.
1 The SMCE[RXB] is set when this buffer is completely Þlled by the CP, indicating the need for the
core to process the buffer. RXB can cause an interrupt if it is enabled.
Table 26-6. SMC UART Errors (Continued)
Error Description