Motorola MPC8260 - Manual (Page 772)

28-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Events that can cause the FCC to interrupt the processor vary slightly among protocols and
are described with each protocol. These events are handled independently for each channel
by the FCC event and mask registers (FCCE and FCCM).
28.8.1 FCC Event Registers (FCCEx)
Each FCC has a 24-bit FCC event register (FCCE) used to report events. On recognition of
an event, the FCC sets its corresponding FCCE bit regardless of the corresponding mask
bit. To the user it appears as a memory-mapped register that can be read at any time. Bits
are cleared by writing ones; writing zeros has no effect on bit values. FCCE is cleared at
reset. Fields of this register are protocol-dependent and are described in the respective
protocol sections.
28.8.2 FCC Mask Registers (FCCMx)
Each FCC has a 24-bit, read/write FCC mask register (FCCM) used to enable or disable CP
interrupts to the core for events reported in an event register (FCCE). Bit positions in
FCCM are identical to those in FCCE. Note that an interrupt is generated only if the FCC
interrupts are also enabled in the SIU; see Section 4.3.1.5, ÒSIU Interrupt Mask Registers
(SIMR_H and SIMR_L).Ó
If an FCCM bit is zero, the CP does not proceed with its usual interrupt handling whenever
that event occurs. Any time a bit in the FCCM register is set, a 1 in the corresponding bit in
the FCCE register sets the FCC event bit in the interrupt pending register; see
Section 4.3.1.4, ÒSIU Interrupt Pending Registers (SIPNR_H and SIPNR_L).Ó
28.8.3 FCC Status Registers (FCCSx)
Each FCC has an 8-bit, read/write FCC status register (FCCS) that lets the user monitor
real-time status conditions (ßags, idle) on the RXD line. It does not show the status of CTS
and CD; their real-time status is available in the appropriate parallel I/O port (see
Chapter 35, ÒParallel I/O PortsÓ).
28.9 FCC Initialization
The FCCs require a number of registers and parameters to be conÞgured after a power-on
reset. The following outline gives the proper sequence for initializing the FCCs, regardless
of the protocol used.
1. Write the parallel I/O ports to conÞgure and connect the I/O pins to the FCCs.
2. Write the appropriate port registers to conÞgure CTS and CD to be parallel I/O with
interrupt capability or to connect directly to the FCC (if modem support is needed).
3. If the TSA is used, the SI must be conÞgured. If the FCC is used in the NMSI mode,
the CPM multiplexing logic (CMX) must still be initialized.
4. Write the GFMR, but do not write the ENT or ENR bits yet.
5. Write the FPSMR.