Motorola MPC8260 - Manual (Page 736)

27-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
channels which uses the slot synchronization. Figure 27-5 shows the SI RAM
programming for the same transparent or HDLC receiver super channels that do not use slot
synchronization.
Figure 27-3. Transmitter Super Channel Example
The example in Figure 27-5 shows a receiver super channel with slot synchronization.
0 1 2 3Р10 11Р13 14 15
MCC LOOP SUPER MCSEL CNT BYT LST
SI RAM Address
1 0 0 0x0 0x1 1 0
1 0 1 0x1 0x0 1
1 First slot of the super channel
1 0
1 0 1 0x2 0x0 2 1 0
1 0 1 0x3 0x7 2
2 Regular (not Þrst) slot of the super channel
0 0
1 0 1 0x4 0x7 2 0 0
1 0 0 0x5 0x1 1 0
1 0 1 0x6 0x7 2 0 0
1 0 1 0x7 0x7 2 0 0
1 0 0 0x8 0x1 1 1
0Р1 2Р9 10Р15
CHANNEL NO
DPR_Base + SCTPBASE +
0x0 Ñ
0x2 0x1
0x4 0x2
0x6 0x2
0x8 0x2
0xA Ñ
0xC 0x1
0xE 0x1
0x10 Ñ
.
The super channel BD tables are associated with channels 1 and 2 (no BD tables are necessary for
SI RAM Super Channel Table
channels 3, 4, 6, and 7)