Motorola MPC8260 - Manual (Page 96)

2-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
2.2.6 Memory Subsystem Support
The processor core supports cache and memory management through separate instruction
and data MMUs (IMMU and DMMU). The processor core also provides dual 16-Kbyte
instruction and data caches, and an efÞcient processor bus interface to facilitate access to
main memory and other bus subsystems. The memory subsystem support functions are
described in the following subsections.
2.2.6.1 Memory Management Units (MMUs)
The processor coreÕs MMUs support up to 4 Petabytes (2 52 ) of virtual memory and
4 Gbytes (2 32 ) of physical memory (referred to as real memory in the PowerPC architecture
speciÞcation) for instructions and data. The MMUs also control access privileges for these
spaces on block and page granularities. Referenced and changed status is maintained by the
processor for each page to assist implementation of a demand-paged virtual memory
system. A key bit is implemented to provide information about memory protection
violations prior to page table search operations.
The LSU calculates effective addresses for data loads and stores, performs data alignment
to and from cache memory, and provides the sequencing for load and store string and
multiple word instructions. The instruction unit calculates the effective addresses for
instruction fetching.
The MMUs translate effective addresses and enforce the protection hierarchy programmed
by the operating system in relation to the supervisor/user privilege level of the access and
in relation to whether the access is a load or store.
2.2.6.2 Cache Units
The processor core provides independent 16-Kbyte, four-way set-associative instruction
and data caches. The cache block size is 32 bytes. The caches are designed to adhere to a
write-back policy, but the processor core allows control of cacheability, write policy, and
memory coherency at the page and block levels. The caches use a least recently used (LRU)
replacement algorithm.
The load/store and instruction fetch units provide the caches with the address of the data or
instruction to be fetched. In the case of a cache hit, the cache returns two words to the
requesting unit.
2.3 Programming Model
The following subsections describe the PowerPC instruction set and addressing modes in
general.
2.3.1 Register Set
This section describes the register organization in the processor core as deÞned by the three
programming environments of the PowerPC architectureÑthe user instruction set
architecture (UISA), the virtual environment architecture (VEA), and the operating