Motorola MPC8260 - Manual (Page 535)

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-11
Part IV. Communications Processor Module
peripheral. When the transfer buffer has fewer than DTS bytes left, the next DREQ
assertion triggers a read of SS_MAX bytes from memory, automatically followed by a
write to the peripheral, and the sequence begins again.
External requests must be enabled (DCM[ERM] = 1) for dual-address peripheral-to-
memory transfers. If DONE is asserted externally by the peripheral or if a
STOP _ IDMA
command is issued, the current transfer is stopped, its BD is closed, and the IDSR[EDN]
or IDSR[SC] event bits are set; see Section 18.8.4, ÒIDMA Event Register (IDSR) and
Mask Register (IDMR).Ó
18.5.2.2 Single Address (Fly-By) Transfers
When DCM[FB] = 1, both peripheral-to-memory and memory-to-peripheral transfers
occur in ßy-by mode; see Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó In fly-by mode,
an internal transfer buffer is not needed because the data is transferred directly between
memory and the peripheral. Also, parameters related to the dual-port RAM bus are not
relevant in ßy-by mode. Each DREQ assertion triggers a transfer the size of the peripheral
port. All transfers are made in single memory accesses accompanied by DACK assertion.
When DONE is asserted externally or a
STOP _ IDMA command is issued, the current transfer
is stopped, its BD is closed, and the IDSR[EDN] or IDSR[SC] event bits are set; see
Section 18.8.4, ÒIDMA Event Register (IDSR) and Mask Register (IDMR).Ó
In ßy-by mode, a peripheral can be conÞgured to handle a burst per DREQ assertion if STS
is programmed to 32. The Þrst phase of the transfer aligns the data to the burst boundary so
that subsequent accesses can be performed in bursts.
18.5.2.2.1 Peripheral-to-Memory Fly-By Transfers
During peripheral-to-memory ßy-by transfers, the IDMA controller writes to memory
while simultaneously asserting DACK. The constant assertion of DACK enables the
controller to write to memory as soon as the peripheral outputs data to the bus. Thus, data
is transferred from a peripheral to memory in one data phase instead of two, increasing
throughput.
For proper operation, STS must equal the peripheral port size.
18.5.2.2.2 Memory-to-Peripheral Fly-By Transfers
During memory-to-peripheral ßy-by transfers, the IDMA controller reads from memory
while simultaneously asserting DACK.
The constant assertion of DACK enables the controller to read from memory as soon as the
peripheral samples the data bus. Thus, data is transferred from memory to a peripheral in
one data phase instead of two, increasing throughput.
For proper operation, DTS must equal the peripheral port size.