Motorola MPC8260 - Manual (Page 634)

22-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
transmission, an underrun must not occur between the DLE and its following character.
This failure mode cannot occur with the MPC8260.
An SCC can be conÞgured as a BISYNC controller to handle basic BISYNC protocol in
normal and transparent modes. The controller can work with the time-slot assigner (TSA)
or nonmultiplexed serial interface (NMSI). The controller has separate transmit and receive
sections whose operations are asynchronous with the core and either synchronous or
asynchronous with other SCCs.
22.1 Features
The following list summarizes features of the SCC in BISYNC mode:
¥ Flexible data buffers
¥ Eight control character recognition registers
¥ Automatic SYNC1ÐSYNC2 detection
¥ 16-bit pattern (bisync)
¥ 8-bit pattern (monosync)
¥ 4-bit pattern (nibblesync)
¥ External SYNC pin support
¥ SYNC/DLE stripping and insertion
¥ CRC16 and LRC (sum check) generation/checking
¥ VRC (parity) generation/checking
¥ Supports BISYNC transparent operation
¥ Maintains parity error counter
¥ Reverse data mode capability
22.2 SCC BISYNC Channel Frame Transmission
The BISYNC transmitter is designed to work with almost no core intervention. When the
transmitter is enabled, it starts sending SYN1ÐSYN2 pairs in the data synchronization
register (DSR) or idles as programmed in the PSMR. The BISYNC controller polls the Þrst
BD in the channelÕs TxBD table. If there is a message to send, the controller fetches the
message from memory and starts sending it after the SYN1ÐSYN2 pair. The entire pair is
always sent, regardless of GSMR[SYNL].
After a buffer is sent, if the last (TxBD[L]) and the Tx block check sequence (TxBD[TB])
bits are set, the BISYNC controller appends the CRC16/LRC and then writes the message
status bits in TxBD status and control Þelds and clears the ready bit, TxBD[R]. It then starts
sending the SYN1ÐSYN2 pairs or idles, according to GSMR[RTSM]. If the end of the
current BD is reached and TxBD[L] is not set, only TxBD[R] is cleared. In both cases, an
interrupt is issued according to TxBD[I]. TxBD[I] controls whether interrupts are generated
after transmission of each buffer, a speciÞc buffer, or each block. The controller then
proceeds to the next BD.