Motorola MPC8260 - Manual (Page 383)

MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-1
Chapter 11
Secondary (L2) Cache Support
110
110
The MPC8260 has features to support an externally controlled secondary (L2) cache such
as the Motorola MPC2605 integrated secondary cache for PowerPC microprocessors. This
chapter describes the MPC8260Õs L2 cache interfaceÑconÞgurations, operation,
programmable parameters, system requirements, and timing.
11.1 L2 Cache ConÞgurations
The MPC8260 supports three L2 cache conÞgurationsÑcopy-back mode, write-through
mode, and ECC/parity mode. The following sections describe the L2 cache modes.
11.1.1 Copy-Back Mode
The use of a copy-back L2 cache offers several advantages over direct access to the memory
system. In copy-back mode, cacheable write operations are performed to the L2 cache
without updating main memory. Since every cacheable write operation does not go to main
memory but to the L2 cache which can be accessed more quickly, write operation latency
is reduced along with contention for the memory system. In copy-back mode, cacheable
read operations that hit in the L2 cache are serviced from the L2 cache without requiring a
memory transaction and its associated latency. Copy-back mode offers the greatest
performance of all the L2 cache modes.
Copy-back L2 cache blocks implement a dirty bit in their tag RAM, which indicates
whether the contents of the L2 cache block have been modiÞed from that in main memory.
During L2 cache line replacement, L2 cache blocks that have been modiÞed (dirty) are
written back to memory; unmodiÞed (not dirty) L2 cache blocks are invalidated and
overwritten without being written back to memory.
Copy-back mode requires that the L2 cache is able to initiate copy-backs to main memory.
To do this, the L2 cache must act as a bus master and implement the bus arbitration signals
BR, BG, and DBG. The MPC8260 can also support additional bus masters (60x or
MPC8260 type) in copy-back mode.
Figure 11-1 shows a MPC8260 connected to a MPC2605 integrated L2 cache in copy-back
mode.