Motorola MPC8260 - Manual (Page 437)

MOTOROLA Chapter 13. Communications Processor Module Overview 13-7
Part IV. Communications Processor Module
13.3.5 Execution from RAM
The CP has an option to execute microcode from a portion of user RAM located in the dual-
port RAM. In this mode, the CP fetches instructions from both the dual-port RAM and its
own private ROM. This mode allows Motorola to add new protocols or enhancements to
the MPC8260 in the form of RAM microcode packages. If preferred, the user can obtain
binary microcode from Motorola and load it into the dual-port RAM.
13.3.6 RISC Controller ConÞguration Register (RCCR)
The RISC controller conÞguration register (RCCR) conÞgures the CP to run microcode
from ROM or RAM and controls the CPÕs internal timer.
19 SCC2 transmit
20 SCC3 receive
21 SCC3 transmit
22 SCC4 receive
23 SCC4 transmit
24 IDMA[1Ð4] emulation (option 2) 1
25 SMC1 receive
26 SMC1 transmit
27 SMC2 receive
28 SMC2 transmit
29 SPI receive
30 SPI transmit
31 I
2
C receive
32 I
2
C transmit
33 RISC timer table
34 IDMA[1Ð4] emulation (option 3) 1
1 The priority of each IDMA channel is programmed independently. See the
RCCR[DRxQP] description in Section 13.3.6, ÒRISC Controller ConÞguration
Register (RCCR).Ó
Table 13-2. Peripheral Prioritization (Continued)
Priority Request