Motorola MPC8260 - Manual (Page 152)

4-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part II. ConÞguration and Reset
Figure 4-9. Interrupt Request Masking
4.2.4 Interrupt Vector Generation and Calculation
Pending unmasked interrupts are presented to the core in order of priority. The interrupt
vector that allows the core to locate the interrupt service routine is made available to the
core by reading SIVEC. The interrupt controller passes an interrupt vector corresponding
to the highest-priority, unmasked, pending interrupt. Table 4-3 lists encodings for the six
low-order bits of the interrupt vector.
Table 4-3. Encoding the Interrupt Vector
Interrupt Number Interrupt Source Description Interrupt Vector
0 Error (No interrupt) 0b00_0000
1 I 2 C 0b00_0001
2 SPI 0b00_0010
3 RISC Timers 0b00_0011
4 SMC1 0b00_0100
5 SMC2 0b00_0101
SCCE
SCCM
13 Input (or
SIPNR
Mask
Bit
SIMR
(Other Unmasked Requests)
Request to
the core
Mask
Bit
Event
Bit
13 Event Bits)