Motorola MPC8260 - Manual (Page 385)

MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-3
Part III. The Hardware Interface
are serviced just as they are for copy-back mode. Write-through mode sacriÞces some of
the write performance of copy-back mode, but guarantees L2 cache coherency with main
memory.
Since write-through mode keeps memory coherent with the contents of the L2 cache, there
is never any need to perform an L2 copy-back. This removes the need for the L2 cache to
maintain a dirty bit in the tag RAM (all cache blocks are unmodiÞed) and it also removes
the need for bus arbitration signals.
The L2 cache is conÞgured for write-through mode by pulling down itÕs WT signal. There
are no conÞguration changes to the MPC8260 required in write-through mode. The
MPC8260 can also support additional bus masters (60x or MPC8260 type) in write-through
mode.
Figure 11-2 shows a MPC8260 connected to a MPC2605 integrated L2 cache in write-
through mode.