Motorola MPC8260 - Manual (Page 501)

MOTOROLA Chapter 15. CPM Multiplexing 15-11
Part IV. Communications Processor Module
Table 15-3 describes CMXSI1CR Þelds.
15.4.3 CMX SI2 Clock Route Register (CMXSI2CR)
The CMX SI2 clock route register (CMXSI2CR) deÞnes the connection of SI2 to the clock
sources that can be input from the bank of clocks.
Bits 0 1 2 3 4 5 6 7
Field RTA1CS RTB1CS RTC1CS RTD1CS TTA1CS TTB1CS TTC1CS TTD1CS
Reset 0000_0000
R/W R/W
Addr 0x11B00
Figure 15-8. CMX SI1 Clock Route Register (CMXSI1CR)
Table 15-3. CMXSI1CR Field Descriptions
Bits Name Description
0 RTA1CS Receive TDM A1 clock source
0 TDM A1 receive clock is CLK1.
1 TDM A1 receive clock is CLK19.
1 RTB1CS Receive TDM B1 clock source
0 TDM B1 receive clock is CLK3.
1 TDM B1 receive clock is CLK9.
2 RTC1CS Receive TDM C1 clock source
0 TDM C1 receive clock is CLK5.
1 TDM C1 receive clock is CLK13.
3 RTD1CS Receive TDM D1 clock source
0 TDM D1 receive clock is CLK7.
1 TDM D1 receive clock is CLK15.
4 TTA1CS Transmit TDM A1 clock source
0 TDM A1 transmit clock is CLK2.
1 TDM A1 transmit clock is CLK20.
5 TTB1CS Transmit TDM B1 clock source
0 TDM B1 transmit clock is CLK4.
1 TDM B1 transmit clock is CLK10.
6 TTC1CS Transmit TDM C1 clock source
0 TDM C1 transmit clock is CLK6.
1 TDM C1 transmit clock is CLK14.
7 TTD1CS Transmit TDM D1 clock source
0 TDM D1 transmit clock is CLK8.
1 TDM D1 transmit clock is CLK16.