Motorola MPC8260 - Manual (Page 384)

11-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Figure 11-1. L2 Cache in Copy-Back Mode
11.1.2 Write-Through Mode
In write-through mode, cacheable write operations are performed to both the L2 cache and
to main memory. Since every cacheable write operation goes to the L2 cache and to main
memory, write operation latency is the same as an ordinary memory write transaction. In
write-through mode, cacheable read operations that hit in the L2 cache are serviced from
the L2 cache without requiring a memory transaction and its associated latency. Thus, reads
BR
DBG
TS, TT[0Ð4], TBST, TSIZ[1Ð3]
A[0Ð31]
CI, WT, GBL, TA, DBB, TEA
CPU_BR, CPU_BG, CPU_DBG
D[0Ð63]
MPC8260
L2BR
L2DBG
TS, TT[0Ð4], TBST, TSIZ[0Ð2]]
CI, WT, GBL, TA, DBB, TEA
AACK, ARTRY AACK, ARTRY
CPU_BR,CPU_BG,CPU_DBG
L2_CLAIM L2_HIT
A[0Ð31]
D[0Ð63]
Memory Controller
SDRAM Main Memory
Latch
MUX
I/O Devices
MPC2605
BG L2BG
TSIZ[0]
(pull down)
(pull up)