Motorola MPC8260 - Manual (Page 464)

14-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Figure 14-6. One TDM Channel with Shadow RAM for Dynamic Route Change
This conÞguration should be chosen when only one TDM is needed, but dynamic rerouting
may be needed on that TDM. Similarly, for two TDM channels, the number of SI
x RAM
entries are reduced for every TDM channel programmed for shadow mode.
14.4.3 Programming SI x RAM Entries
The programming of each entry in the SI x RAM determines the routing of the serial bits (or
bit groups) and the assertion of strobe outputs. If MCC is set, the entry refers to the
corresponding MCC; otherwise, it refers to other serial controllers. Figure 14-7 shows the
entry Þelds for both cases.
When MCC = 0, the SI x RAM entry Þelds function as described in Table 14-1.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field MCC = 0 SWTR SSEL1 SSEL2 SSEL3 SSEL4 0 CSEL CNT BYT LST
MCC = 1 LOOP/ECHO SUPER MCSEL CNT BYT LST
R/W R/W
Addr See Chapter 3, ÒMemory Map.Ó
Figure 14-7. SI x RAM Entry Fields
128 Entries
TXa
Route
Framing Signals
L1TCLKa x
L1TSYNCa x
SI x RAM Address:
128 Entries
RXa
Route
255
1279
1024
L1RCLKa x
L1RSYNCa x
1280
256
511
1535
(16 Bits Wide)
0