Motorola MPC8260 - Manual (Page 112)

2-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
Although exceptions have other characteristics as well, such as whether they are maskable
or nonmaskable, the distinctions shown in Table 2-4 deÞne categories of exceptions that the
processor core handles uniquely. Note that Table 2-4 includes no synchronous imprecise
instructions.
The processor coreÕs exceptions, and conditions that cause them, are listed in Table 2-5.
Table 2-4. Exception Classifications for the Processor Core
Synchronous/Asynchronous Precise/Imprecise Exception Type
Asynchronous, nonmaskable Imprecise Machine check
System reset
Asynchronous, maskable Precise External interrupt
Decrementer
System management interrupt
Synchronous Precise Instruction-caused exceptions
Table 2-5. Exceptions and Conditions
Exception
Type
Vector Offset
(hex)
Causing Conditions
Reserved 00000 Ñ
System reset 00100 A system reset is caused by the assertion of either SRESET or HRESET. Note that
the reset value of the MSR exception preÞx bit (MSR[IP]), described in the
MPC603e UserÕs Manual, is determined by the CIP bit in the hard reset
conÞguration word. This is described in Section 5.4.1, ÒHard Reset ConÞguration
Word.Ó
Machine check 00200 A machine check is caused by the assertion of the TEA signal during a data bus
transaction, assertion of MCP, or an address or data parity error.
DSI 00300 The cause of a DSI exception can be determined by the bit settings in the DSISR,
listed as follows:
1 Set if the translation of an attempted access is not found in the primary hash
table entry group (HTEG), or in the rehashed secondary HTEG, or in the range
of a DBAT register; otherwise cleared.
4 Set if a memory access is not permitted by the page or DBAT protection
mechanism; otherwise cleared.
5 Set by an eciwx or ecowx instruction if the access is to an address that is
marked as write-through, or execution of a load/store instruction that accesses a
direct-store segment.
6 Set for a store operation and cleared for a load operation.
11 Set if eciwx or ecowx is used and EAR[E] is cleared.