Motorola MPC8260 - Manual (Page 37)

MOTOROLA Illustrations xxxvii
ILLUSTRATIONS
Figure
Number
Title
Page
Number
10-82 Refresh Cycle (CBR) to EDO DRAM................................................................... 10-98
10-83 Exception Cycle For EDO DRAM ........................................................................ 10-99
10-84 Pipelined Bus Operation and Memory Access in 60x-Compatible Mode........... 10-103
10-85 External Master Access (GPCM) ........................................................................ 10-104
10-86 External Master Configuration with SDRAM Device......................................... 10-105
11-1 L2 Cache in Copy-Back Mode ................................................................................ 11-2
11-2 External L2 Cache in Write-Through Mode............................................................ 11-4
11-3 External L2 Cache in ECC/Parity Mode ................................................................. 11-6
11-4 Read Access with L2 Cache .................................................................................... 11-9
12-1 Test Logic Block Diagram....................................................................................... 12-2
12-2 TAP Controller State Machine ................................................................................ 12-3
12-3 Output Pin Cell (O.Pin) ........................................................................................... 12-4
12-4 Observe-Only Input Pin Cell (I.Obs)....................................................................... 12-4
12-5 Output Control Cell (IO.CTL) ................................................................................. 12-5
12-6 General Arrangement of Bidirectional Pin Cells..................................................... 12-5
13-1 MPC8260 CPM Block Diagram .............................................................................. 13-3
13-2 Communications Processor (CP) Block Diagram ................................................... 13-5
13-3 RISC Controller Configuration Register (RCCR) ................................................... 13-8
13-4 RISC Time-Stamp Control Register (RTSCR)........................................................ 13-9
13-5 RISC Time-Stamp Register (RTSR) ..................................................................... 13-10
13-6 CP Command Register (CPCR)............................................................................. 13-11
13-7 Dual-Port RAM Block Diagram ............................................................................ 13-15
13-8 Dual-Port RAM Memory Map .............................................................................. 13-16
13-9 RISC Timer Table RAM Usage ............................................................................ 13-19
13-10 RISC Timer Command Register (TM_CMD) ....................................................... 13-20
13-11 TM_CMD Field Descriptions................................................................................ 13-21
13-12 RISC Timer Event Register (RTER)/Mask Register (RTMR).............................. 13-21
14-1 SI Block Diagram .................................................................................................... 14-2
14-2 Various Configurations of a Single TDM Channel ................................................. 14-5
14-3 Dual TDM Channel Example .................................................................................. 14-6
14-4 Enabling Connections to the TSA ........................................................................... 14-8
14-5 One TDM Channel with Static Frames and Independent Rx and Tx Routes .......... 14-9
14-6 One TDM Channel with Shadow RAM for Dynamic Route Change ................... 14-10
14-7 SIx RAM Entry Fields ........................................................................................... 14-10
14-8 Using the SWTR Feature....................................................................................... 14-12
14-9 Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size ....... 14-16
14-10 SI Global Mode Registers (SIxGMR) ................................................................... 14-17
14-11 SI Mode Registers (SIxMR) .................................................................................. 14-18
14-12 One-Clock Delay from Sync to Data (xFSD = 01)................................................ 14-20
14-13 No Delay from Sync to Data (xFSD = 00) ............................................................ 14-20
14-14 Falling Edge (FE) Effect When CE = 1 and xFSD = 01 ....................................... 14-21
14-15 Falling Edge (FE) Effect When CE = 0 and xFSD = 01 ....................................... 14-21
14-16 Falling Edge (FE) Effect When CE = 1 and xFSD = 00 ....................................... 14-22