Motorola MPC8260 - Manual (Page 380)

10-104 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Figure 10-85 shows the 1-cycle delay for external master access. For systems that use the
60x bus with low frequency (33 MHz), the 1-cycle delay for external masters can be
eliminated by setting BCR[EXDD].
Figure 10-85. External Master Access (GPCM)
10.9.6.1 Example of External Master Using the SDRAM Machine
Figure 10-86 shows an interconnection in which a 60x-compatible external master and the
MPC8260 can share access to a SDRAM bank. Note that the address multiplexer is
controlled by SDAMUX, while the address latch is controlled by ALE. Also note that
because this is a 64-bit port size SDRAM, BADDR is not needed.
CLKIN
A[0–28]
A[27–31]
TT
TBST
TSIZ
TS
TA
CS
WE
OE
Data
Address
Match and
Compare
Memory
Device
Access