Motorola MPC8260 - Manual (Page 478)

14-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Table 14-6 describes SIxRSR Þelds.
14.5.4 SI Command Register (SIxCMDR)
The SI command registers (SIxCMDR), shown in Figure 14-19, allow the user to
dynamically program the SIx RAM. When the user sets bits in the SIxCMDR, the SIx
switches to the shadow SIx RAM at the end of the current-route RAM programming frame.
For more information about dynamic programming, see Section 14.4.5, ÒStatic and
Dynamic Routing.Ó
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ SSADA Ñ SSADB Ñ SSADC Ñ SSADD
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11B2E (SI1RSR), 0x11B4E (SI2RSR)
Figure 14-18. SIx RAM Shadow Address Registers (SIxRSR)
Table 14-6. SIxRSR Field Descriptions
Bits Name Description
0, 4, 8,
12 Ñ Reserved. Should be cleared.
1Р3,
5Р7,
9Р11,
13Р15 SSADx Starting bank address for the shadow RAM of TDM a, b, c, or d. DeÞnes the starting bank
address of the shadow SIx RAM section that belongs to the corresponding TDM channel.
Note: As noted before, the SIx RAM contain four banks of 64 entries for receive and four banks of
64 entries for transmit.
In spite of the above, the starting bank address of each TDM can be programmed by the user in
a granularity of 32 entries, but the user cannot put two different TDMs on the same bank.
The user can put the shadow RAM section of the same TDM on the same bank.
The last entry of a certain TDM frame is determined by the LST bit in the SIx RAM entry. The
user must set this bit within the entries of SIx RAM shadow blocks for every TDM used. That
means before the starting address of the next TDM.
Bits 0 1 2 3 4 5 6 7
Field CSRRA CSRTA CSRRB CSRTB CSRRC CSRTC CSRRD CSRTD
Reset 0000_0000
R/W R/W
Addr 0x11B2A (SI1CMDR), 0x11B4A (SI2CMDR)
Figure 14-19. SI Command Register (SIxCMDR)