Motorola MPC8260 - Manual (Page 366)

10-90 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
¥ If GPL_4 is not used as an output, the performance for a page read access can be
improved by setting MxMR[GPL_x4DIS]. The following example shows how the
burst read access to FPM DRAM (no LOOP) can be modiÞed using this feature. In
this case the conÞguration registers are deÞned in the following way.
The timing diagram in Figure 10-75 shows how the burst-read access shown in
Figure 10-70 can be reduced.
Table 10-42. UPMs Attributes Example
Explanation Field Value
Machine select UPMA BRx[MS] 0b100
Port size 64-bit BRx[PS] 0b00
No write protect (R/W) BRx[WP] 0b0
Refresh timer value (1024 refresh cycles) PURT[PURT] 0x0C
Refresh timer enable MxMR[RFEN] 0b1
Address multiplex size MxMR[AMx] 0b010
Disable timer period MxMR[DSx] 0b01
Select between GPL4 and Wait = Wait, data sampled at clock negative edge MxMR[GPL_x4DIS] 0b1
Burst inhibit device ORx[BI] 0b0