Motorola MPC8260 - Manual (Page 72)

1-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
Ñ PowerPC architecture-compliant memory management unit (MMU)
Ñ Common on-chip processor (COP) test interface
Ñ Supports bus snooping for cache coherency
Ñ No ßoating-point unit (FPU). Floating-point arithmetic is not supported.
Ñ Support for ßoating-point loads and stores.
Ñ Support for cache locking.
¥ Low-power (less than 2.5 W when fully operational at 133 MHz, 2-V internal and
3.3-V I/O)
¥ Separate power supply for internal logic (2 V) and for I/O (3.3 V)
¥ Separate PLLs for PowerPC core and for the CPM
Ñ PowerPC core and CPM can run at different frequencies for power/performance
optimization
Ñ Internal PowerPC core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1,
3.5:1, 4:1, 5:1, 6:1 ratios
Ñ Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1,
6:1 ratios
¥ 64-bit data and 32-bit address 60x bus
Ñ Bus supports multiple master designs
Ñ Supports single transfers and burst transfers
Ñ 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
Ñ Supports data parity or ECC and address parity
¥ 32-bit data and 18-bit address local bus
Ñ Single-master bus, supports external slaves
Ñ Eight-beat burst transfers
Ñ 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
¥ System interface unit (SIU)
Ñ Clock synthesizer
Ñ Reset controller
Ñ Real-time clock (RTC) register
Ñ Periodic interrupt timer
Ñ Hardware bus monitor and software watchdog timer
Ñ IEEE 1149.1 JTAG test access port
¥ Twelve-bank memory controller
Ñ Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and
other user-deÞnable peripherals