Motorola MPC8260 - Manual (Page 388)

11-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Figure 11-3. External L2 Cache in ECC/Parity Mode
TS, TT[0Ð4], TBST
A[0Ð31]
CI, GBL, TA, DBB, TEA
CPU_BR, CPU_BG, CPU_DBG
D[0Ð63],DP[0Ð7]
MPC8260
TS, TT[0Ð4], TBST
CI, GBL, TA, DBB, TEA
AACK, ARTRY AACK, ARTRY
CPU_BR,CPU_BG,CPU_DBG
L2_CLAIM L2_HIT
A[0Ð28]
D[0Ð63], DP[0Ð7]
Memory Controller
SDRAM Main Memory
Latch
MUX
I/O Devices
MPC2605
TSIZE[0]
(pull down)
WT
(pull down)
TSIZ[0Ð2]
(pull downs)
A[29Ð31]
(pull downs)
BR
DBG
L2BR
L2DBG
BG L2BG
(pull up) (pull up)