Motorola MPC8260 - Manual (Page 862)

29-82 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
29.12 The UTOPIA Interface
The ATM controller interfaces with a PHY device through the UTOPIA interface. The
MPC8260 supports UTOPIA level 2 for both master and slave modes.
29.12.1 UTOPIA Interface Master Mode
UTOPIA master signals are shown in Figure 29-57.
Figure 29-57. UTOPIA Master Mode Signals
Table 29-44 describes UTOPIA master mode signals.
0x0C INTQ_ENTRY Word Interrupt queue entry. Must be zero. Note that when an overrun occurs, this
entry must be cleared again.
1 Offset from INTT_BASE+RCT/TCT[INTQ] ´ 16
Table 29-44. UTOPIA Master Mode Signal Descriptions
Signal Description
TxDATA[0Р15]/
[0Р7] Carries transmit data from the ATM controller to a PHY device. TxDATA[15]/[7] is the msb when using
UTOPIA 16/8, TxDATA[0] is the lsb.
TxSOC Transmit start of cell. Asserted by the ATM controller when the Þrst byte of a cell is sent on TxDATA
lines.
TxENB Transmit enable. Asserted by the ATM controller when valid data is placed on the TxDATA lines.
TxCLAV[0Ð3] Transmit cell available. Asserted by the PHY device to indicate that the PHY has room for a complete
cell.
TxPRTY Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA bits.
TxCLK Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB, TxCLAV,
TxPRTY signals. All the above signals are sampled at low-to-high transitions of TxCLK.
TxADD[0Ð4] Transmit address. Address bus from the ATM controller to the PHY device used to select the
appropriate M-PHY device. Each M-PHY device needs to maintain its address. TxADD[4] is the msb.
Table 29-43. Interrupt Queue Parameter Table (Continued)
Offset 1 Name Width Description
TXDATA[0Р15]/[0Р7]
TxSOC
TXENB
TXPRTY
TXCLK
TXCLAV[0Ð3]
TXADD[0Ð4]
MPC8260
RXDATA[0Р15]/[0Р7]
RXSOC
RXENB
RXPRTY
RXCLK
RXCLAV[0Ð3]
RXADD[0Ð4]
MPC8260