Interrupt circular table entry -20 – Motorola MPC8260 User Manual
Page 750
27-20
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
Table 27-14 describes interrupt circular table Þelds.
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
V
W
Ñ
UN
TXB
Ñ
NID
IDL
MRF RXF
BSY
RXB
R/W
R/W
Bits
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
Ñ
Channel Number
0
0
0
0
0
0
R/W
R/W
Figure 27-14. Interrupt Circular Table Entry
Table 27-14. Interrupt Circular Table Entry Field Descriptions
Bits
Name
Description
0
V
Valid bit. V = 1 indicates that this entry contains valid interrupt information. Upon generating a new
entry, the CP sets V = 1. The user clears V immediately after it reads the interrupt ßags of the entry
(before processing the interrupt). The V bits in the table are user-initialized. During initialization, the
user must clear those bits in all table entries.
1
W
Wrap bit. W = 1 indicates the last interrupt circular table entry. The next eventÕs entry is written/read
(by CP/user) from the address contained in INTBASE (see Table 27-1). During initialization, the user
must clear all W bits in the table except for the last one which must be set.
2Р5
С
Reserved, should be cleared.
6
UN
Tx no data. The CP sets this ßag if there is no data available to be sent to the transmitter. The
transmitter sends an ABORT indication and then sends idles.
7
TXB
Tx buffer. A buffer has been completely transmitted. TXB is set (and an interrupt request is
generated) as soon as the programmed number of PAD characters (or the closing ßag, for PAD = 0)
is written to MCC transmit FIFO. This controls when the TXB interrupt is given in relation to the
closing ßag sent out at TXD. Section 27.11.2, ÒTransmit Buffer Descriptor (TxBD)Ó describes how
PAD characters are used.
8Р9
С
Reserved, should be cleared.
10
MRF
Maximum receive frame length violation. This interrupt occurs in HDLC mode when more bytes are
received than the value speciÞed in MFLR. This interrupt is generated as soon as the MFLR value is
exceeded; the remainder of the frame is discarded
11
NID
Set whenever a pattern that is not an idle pattern is identiÞed.
12
IDL
Idle. Set when the channelÕs receiver identiÞes the Þrst occurrence of HDLC idle (0xFFFE) after any
non-idle pattern.
13
RXF
Rx frame. A complete HDLC frame has been received.
14
BSY
Busy. A frame was received but was discarded due to lack of buffers.
15
RXB
Rx buffer. A buffer has been received on this channel that was not the last buffer in frame. This
interrupt is also given for different error types that can happen during reception. Error conditions are
reported in the RxBD.
16Р18 С
Reserved, should be cleared.
19Ð26 CN
Channel number. IdentiÞes the requests channel index (0Р255).
27Р31 С
Reserved, should be cleared.