beautypg.com

8 smc transparent rxbd, Smc transparent rxbd -26, Smc transparent rxbd field descriptions -26 – Motorola MPC8260 User Manual

Page 722

background image

26-26

MPC8260 PowerQUICC II UserÕs Manual

MOTOROLA

Part IV. Communications Processor Module

26.4.8 SMC Transparent RxBD

Using BDs, the CP reports information about the received data for each buffer and closes
the current buffer, generates a maskable interrupt, and starts to receive data into the next
buffer after one of the following events:

¥

An overrun error occurs.

¥

A full receive buffer is detected.

¥

The

ENTER

HUNT

MODE

command is issued.

Table 26-13 describes SMC transparent RxBD Þelds.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Offset + 0

E

Ñ

W

I

Ñ

CM

Ñ

OV

Ñ

Offset + 2

Data Length

Offset + 4

Rx Data Buffer Pointer

Offset + 6

Figure 26-13. SMC Transparent RxBD

Table 26-13. SMC Transparent RxBD Field Descriptions

Bits

Name

Description

0

E

Empty.
0 The buffer is full or reception was aborted due to an error. The core can read or write any Þelds of

this RxBD. The CP does not use this BD while E = 0.

1 The buffer is empty or is receiving data. The CP owns this RxBD and its buffer. Once E is set, the

core should not write any Þelds of this RxBD.

1

Ñ

Reserved, should be cleared.

2

W

Wrap (last BD in RxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that

RBASE points to. The number of RxBDs is determined only by the W bit and overall space
constraints of the dual-port RAM.

3

I

Interrupt.
0 No interrupt is generated after this buffer is Þlled.
1 SMCE[RXB] is set when the CP completely Þlls this buffer indicating that the core must process the

buffer. The RXB bit can cause an interrupt if it is enabled.

4Р5

С

Reserved, should be cleared.

6

CM

Continuous mode.
0 Normal operation.
1 The CP does not clear E after this BD is closed, allowing the buffer to be overwritten when the CP

next accesses this BD. However, E is cleared if an error occurs during reception, regardless of how
CM is set.

7Р13 С

Reserved, should be cleared.

14

OV

Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received
data is placed into the buffer.

15

Ñ

Reserved, should be cleared.