NXP Semiconductors LPC24XX UM10237 - Manual (Page 87)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 87 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.16 Dynamic Memory Active Bank A to Active Bank B Time register
(EMCDynamictRRD - 0xFFE0 8054)
The EMCDynamicTRRD register enables you to program the active bank A to active bank
B latency, tRRD. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tRRD. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–83 shows the bit assignments for the EMCDynamicTRRD register.
10.17 Dynamic Memory Load Mode register to Active Command Time
(EMCDynamictMRD - 0xFFE0 8058)
The EMCDynamicTMRD register enables you to program the load mode register to active
command time, tMRD. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tMRD, or tRSA. This register is
accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selectsmust be programmed.
Table 5–84 shows the bit assignments for the EMCDynamicTMRD register.
Table 82. Dynamic Memory Exit Self-refresh register (EMCDynamictXSR - address
0xFFE0 8050) bit description
Bit Symbol Value Description Reset
Value
4:0 Exit self-refresh
to active
command time
(tXSR) 0x0 -
0x1E n + 1 clock cycles. The delay is in CCLK cycles. 0x1F
0xF 32 clock cycles (POR reset value).
31:5 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
Table 83. Dynamic Memory Acitve Bank A to Active Bank B Time register
(EMCDynamictRRD - address 0xFFE0 8054) bit description
Bit Symbol Value Description Reset
Value
3:0 Active bank A to
active bank B
latency (tRRD ) 0x0 -
0xE n + 1 clock cycles. The delay is in CCLK cycles. 0xF
0xF 16 clock cycles (POR reset value).
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA