NXP Semiconductors LPC24XX UM10237 - Manual (Page 577)

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User manual Rev. 04 — 26 August 2009 577 of 792
NXP Semiconductors
UM10237
Chapter 22: LPC24XX I 2 C interfaces I 2 C0/1/2
6.4 Slave Transmitter mode
The first byte is received and handled as in the slave receiver mode. However, in this
mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via
SDA while the serial clock is input through SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer. In a given application, I
2 C may
operate as a master and as a slave. In the slave mode, the I 2 C hardware looks for its own
slave address and the general call address. If one of these addresses is detected, an
interrupt is requested. When the microcontrollers wishes to become the bus master, the
hardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, the I
2 C
interface switches to the slave mode immediately and can detect its own slave address in
the same serial transfer.
7. I 2 C implementation and operation
7.1 Input filters and output stages
Input signals are synchronized with the internal clock , and spikes shorter than three
clocks are filtered out.
The output for I 2 C is a special pad designed to conform to the I 2 C specification. The
outputs for I2C1 and I2C2 are standard port I/Os that support a subset of the full I 2 C
specification.
Figure 22–117 shows how the on-chip I 2 C bus interface is implemented, and the following
text describes the individual blocks.
Fig 116. Format of Slave Transmitter mode
DATA
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
A DATA
data transferred
(n Bytes + Acknowledge)
“0” - write
“1” - read
from Master to Slave
from Slave to Master
S SLAVE ADDRESS R A P A