Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
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UM10237_4
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User manual
Rev. 04 — 26 August 2009
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NXP Semiconductors
UM10237
Chapter 11: LPC24XX Ethernet
7.1.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0xFFE0 0008)
The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0xFFE0 0008. Its
bit definition is shown in
.
7.1.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0xFFE0 000C)
The Non Back-to-Back Inter-Packet-Gap register (IPGR) has an address of
0xFFE0 000C. Its bit definition is shown in
7.1.5 Collision Window / Retry Register (CLRT - 0xFFE0 0010)
The Collision window / Retry register (CLRT) has an address of 0xFFE0 0010. Its bit
definition is shown in
Table 190. Back-to-back Inter-packet-gap register (IPGT - address 0xFFE0 0008) bit description
Bit
Symbol
Function
Reset
value
6:0
BACK-TO-BACK
INTER-PACKET-GAP
This is a programmable field representing the nibble time offset of the minimum
possible period between the end of any transmitted packet to the beginning of the
next. In Full-Duplex mode, the register value should be the desired period in
nibble times minus 3. In Half-Duplex mode, the register value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is
0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or
9.6 µs (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d),
which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs
(in 10 Mbps mode).
0x0
31:7
-
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
0x0
Table 191. Non Back-to-back Inter-packet-gap register (IPGR - address 0xFFE0 000C) bit description
Bit
Symbol
Function
Reset
value
6:0
NON-BACK-TO-BACK
INTER-PACKET-GAP PART2
This is a programmable field representing the Non-Back-to-Back
Inter-Packet-Gap. The recommended value is 0x12 (18d), which
represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in
10 Mbps mode).
0x0
7
-
Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
0x0
14:8
NON-BACK-TO-BACK
INTER-PACKET-GAP PART1
This is a programmable field representing the optional carrierSense
window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is
detected during the timing of IPGR1, the MAC defers to carrier. If,
however, carrier becomes active after IPGR1, the MAC continues timing
IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x0 to IPGR2. The recommended
value is 0xC (12d)
0x0
31:15 -
Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
0x0