Power domains, Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
Page 66
UM10237_4
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 04 — 26 August 2009
66 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
[1]
LPC247x only.
3.4.10 Power control usage notes
After every reset, the PCONP register contains the value that enables selected interfaces
and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user’s application might have to access
the PCONP in order to start using some of the on-board peripherals.
Power saving oriented systems should have ones in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
4.
Power domains
The LPC2400 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the Real Time Clock and the
Battery RAM.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation. Details may be found in
.
Remark: The RTC and the battery RAM operate independently from each other.
Therefore, the battery RAM can be accessed at any time, regardless of whether the RTC
is enabled or disabled via a dedicated bit in the PCONP register.
22
PCTIM2
Timer 2 power/clock control bit.
0
23
PCTIM3
Timer 3 power/clock control bit.
0
24
PCUART2
UART 2 power/clock control bit.
0
25
PCUART3
UART 3 power/clock control bit.
0
26
PCI2C2
I
2
S interface 2 power/clock control bit.
1
27
PCI2S
I
2
S interface power/clock control bit.
0
28
PCSDC
SD card interface power/clock control bit.
0
29
PCGPDMA GP DMA function power/clock control bit.
0
30
PCENET
Ethernet block power/clock control bit.
0
31
PCUSB
USB interface power/clock control bit.
0
Table 63.
Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description
Bit
Symbol
Description
Reset
value