Tables, Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual

Page 761

UM10237_4

User manual

Rev. 04 — 26 August 2009

761 of 792

NXP Semiconductors

UM10237

Chapter 36: LPC24XX Supplementary information

Tables

Table 1.

LPC24XX overview. . . . . . . . . . . . . . . . . . . . . . .3

Table 2.

Differences between LPC2400 parts . . . . . . . . .4

Table 3.

LPC2458 ordering information . . . . . . . . . . . . . .6

Table 4.

LPC2458 ordering options . . . . . . . . . . . . . . . . .6

Table 5.

LPC2420/60 ordering information . . . . . . . . . . .6

Table 6.

LPC2420/60 ordering options . . . . . . . . . . . . . .7

Table 7.

LPC2468 ordering information . . . . . . . . . . . . . .7

Table 8.

LPC2468 ordering options . . . . . . . . . . . . . . . . .7

Table 9.

LPC2470 ordering information . . . . . . . . . . . . . .7

Table 10. LPC2470 ordering options . . . . . . . . . . . . . . . . .8
Table 11. LPC2478 ordering information . . . . . . . . . . . . . .8
Table 12. LPC2478 ordering options . . . . . . . . . . . . . . . . .8
Table 13. LPC2400 memory options and addressing. . . .16
Table 14. LPC2458 memory usage and details . . . . . . . .16
Table 15. LPC2420/60/70 memory usage and details . . .17
Table 16. LPC2468/78 memory usage and details. . . . . .17
Table 17. APB peripherals and base addresses . . . . . . .21
Table 18. ARM exception vector locations . . . . . . . . . . . .22
Table 19. LPC2400 Memory mapping modes . . . . . . . . .23
Table 20. Memory mapping control registers . . . . . . . . . .24
Table 21. Memory Mapping control register (MEMMAP -

address 0xE01F C040) bit description . . . . . . .24

Table 22. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 23. Summary of system control registers . . . . . . . .27
Table 24. External Interrupt registers . . . . . . . . . . . . . . . .28
Table 25. External Interrupt Flag register (EXTINT - address

0xE01F C140) bit description . . . . . . . . . . . . . .29

Table 26. External Interrupt Mode register (EXTMODE -

address 0xE01F C148) bit description . . . . . . .30

Table 27. External Interrupt Polarity register (EXTPOLAR -

address 0xE01F C14C) bit description . . . . . . .31

Table 28. Reset Source Identification register (RSID -

address 0xE01F C180) bit description . . . . . . .34

Table 29. AHB configuration register map . . . . . . . . . . . .34
Table 30. AHB Arbiter Configuration register 1 (AHBCFG1 -

address 0xE01F C188) bit description . . . . . . .35

Table 31. Priority sequence (bit 0 = 0): LCD, CPU, GPDMA,

AHB1, USB . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 32. Priority sequence (bit 0 = 0): USB, AHB1, CPU,

GPDMA, LCD . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 33. Priority sequence (bit 0 = 0): GPDMA, AHB1,

CPU, LCD, USB . . . . . . . . . . . . . . . . . . . . . . . .36

Table 34. Priority sequence (bit 0 = 0): USB, LCD, AHB1,

CPU, GPDMA . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 35. AHB Arbiter Configuration register 2 (AHBCFG2 -

address 0xE01F C18C) bit description . . . . . . .37

Table 36. Priority sequence (bit 0 = 0): Ethernet, CPU . .38
Table 37. Priority sequence (bit 0 = 0): Ethernet, CPU . .38
Table 38. System Controls and Status register (SCS -

address 0xE01F C1A0) bit description . . . . . . .38

Table 39. Recommended values for C

X1/X2

in oscillation

mode (crystal and external components
parameters) low frequency mode (OSCRANGE =
0, see

Table 3–38

) . . . . . . . . . . . . . . . . . . . . . .44

Table 40. Recommended values for C

X1/X2

in oscillation

mode (crystal and external components

parameters) high frequency mode (OSCRANGE =
1, see

Table 3–38

) . . . . . . . . . . . . . . . . . . . . . . 44

Table 41. Summary of system control registers. . . . . . . . 45
Table 42. Clock Source Select register (CLKSRCSEL -

address 0xE01F C10C) bit description . . . . . . 46

Table 43. PLL registers . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 44. PLL Control register (PLLCON - address

0xE01F C080) bit description. . . . . . . . . . . . . . 49

Table 45. PLL Configuration register (PLLCFG - address

0xE01F C084) bit description. . . . . . . . . . . . . . 49

Table 46. Multiplier values for a 32 kHz oscillator . . . . . . 50
Table 47. PLL Status register (PLLSTAT - address

0xE01F C088) bit description. . . . . . . . . . . . . . 52

Table 48. PLL control bit combinations . . . . . . . . . . . . . . 52
Table 49. PLL Feed register (PLLFEED - address

0xE01F C08C) bit description . . . . . . . . . . . . . 53

Table 50. PLL frequency parameter . . . . . . . . . . . . . . . . 53
Table 51. Additional Multiplier Values for use with a Low

Frequency Clock Input . . . . . . . . . . . . . . . . . . . 54

Table 52. Potential values for PLL example . . . . . . . . . . 56
Table 53. CPU Clock Configuration register (CCLKCFG -

address 0xE01F C104) bit description. . . . . . . 57

Table 54. USB Clock Configuration register (USBCLKCFG -

address 0xE01F C108) bit description. . . . . . . 58

Table 55. IRC Trim register (IRCTRIM - address

0xE01F C1A4) bit description . . . . . . . . . . . . . 58

Table 56. Peripheral Clock Selection register 0 (PCLKSEL0

- address 0xE01F C1A8) bit description . . . . . 58

Table 57. Peripheral Clock Selection register 1 (PCLKSEL1

- address 0xE01F C1AC) bit description . . . . . 59

Table 58. Peripheral Clock Selection register bit values . 60
Table 59. Power Control registers . . . . . . . . . . . . . . . . . . 62
Table 60. Power Mode Control register (PCON - address

0xE01F C0C0) bit description . . . . . . . . . . . . . 62

Table 61. Encoding of reduced power modes . . . . . . . . . 63
Table 62. Interrupt Wakeup register (INTWAKE - address

0xE01F C144) bit description. . . . . . . . . . . . . . 64

Table 63. Power Control for Peripherals register (PCONP -

address 0xE01F C0C4) bit description . . . . . . 65

Table 64. EMC configuration . . . . . . . . . . . . . . . . . . . . . . 68
Table 65. Memory bank selection

[1]

. . . . . . . . . . . . . . . . . 73

Table 66. Pad interface and control signal descriptions . 74
Table 67. Summary of EMC registers . . . . . . . . . . . . . . . 75
Table 68. EMC Control register (EMCControl - address

0xFFE0 8000) bit description . . . . . . . . . . . . . . 77

Table 69. EMC Status register (EMCStatus - address

0xFFE0 8008) bit description . . . . . . . . . . . . . . 78

Table 70. EMC Configuration register (EMCConfig -

address 0xFFE0 8008) bit description . . . . . . . 79

Table 71. Dynamic Control register (EMCDynamicControl -

address 0xFFE0 8020) bit description . . . . . . . 79

Table 72. Dynamic Memory Refresh Timer register

(EMCDynamicRefresh - address 0xFFE0 8024)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 73. Dynamic Memory Read Configuration register

(EMCDynamicReadConfig - address