NXP Semiconductors LPC24XX UM10237 - Manual (Page 55)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 55 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
3. Choose a value for the PLL input frequency (F
IN
). This can be a clock obtained from
the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support,
the main oscillator should be used.
4. Calculate values for M and N to produce a sufficiently accurate F
CCO
frequency. The
desired M value -1 will be written to the MSEL field in PLLCFG. The desired N value -1
will be written to the NSEL field in PLLCFG.
In general, it is better to use a smaller value for N, to reduce the level of multiplication that
must be accomplished by the CCO. Due to the difficulty in finding the best values in some
cases, it is recommended to use a spreadsheet or similar method to show many
possibilities at once, from which an overall best choice may be selected. A spreadsheet is
available from NXP for this purpose.
3.2.13 Examples of PLL settings
The following examples illustrate selecting PLL values based on different system
requirements.
Example 1)
Assumptions:
• The USB interface will be used in the application. The lowest integer multiple of
96 MHz that falls within the PLL operating range (288 MHz) will be targeted.
• The desired CPU rate = 60 MHz.
• An external 4 MHz crystal or clock source will be used as the system clock source.
Calculations:
M = (F
CCO
× N) / (2 × F
IN
)
Start by assuming N = 1, since this produces the smallest multiplier needed for the PLL.
So, M = 288
Ч 10 6 / (2
Ч 4 Ч 10 6 ) = 36. Since the result is an integer, there is no need to
look further for a good set of PLL configuration values. The value written to PLLCFG
would be 0x23 (N - 1 = 0; M - 1 = 35 = 0x23).
The potential CPU clock rate can be determined by dividing F
CCO
by the desired CPU
frequency: 288
Ч 10 6 / 60
Ч 10 6 = 4.8. The nearest integer value for the CPU Clock
Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
If it is important to obtain exactly 60 MHz, an F
CCO
rate must be found that can be divided
down to both 48 MHz and 60 MHz. The only possibility is 480 MHz. Divided by 10, this
gives the 48 MHz with a 50% duty cycle needed by the USB block. Divided by 8, it gives
60 MHz for the CPU clock. PLL settings for 480 MHz are N = 1 and M = 60.
Example 2)
Assumptions:
• The USB interface will not be used in the application.
• The desired CPU rate = 72 MHz
• The 32.768 kHz RTC clock source will be used as the system clock source
Calculations: