NXP Semiconductors LPC24XX UM10237 - Manual (Page 784)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 784 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
5 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Chapter 17: LPC24XX UART1
1 Basic configuration . . . . . . . . . . . . . . . . . . . . 443
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 444
4 Register description . . . . . . . . . . . . . . . . . . . 444
4.1 UART1 Receiver Buffer Register (U1RBR -
0xE001 0000, when DLAB = 0 Read Only) . 447
4.2 UART1 Transmitter Holding Register (U1THR -
0xE001 0000 when DLAB = 0, Write Only) . 447
4.3 UART1 Divisor Latch LSB and MSB Registers
(U1DLL - 0xE001 0000 and U1DLM -
0xE001 0004, when DLAB = 1) . . . . . . . . . . 447
4.4 UART1 Interrupt Enable Register (U1IER -
0xE001 0004, when DLAB = 0) . . . . . . . . . . 448
4.5 UART1 Interrupt Identification Register (U1IIR -
0xE001 0008, Read Only) . . . . . . . . . . . . . . 449
4.6 UART1 FIFO Control Register (U1FCR -
0xE001 0008, Write Only). . . . . . . . . . . . . . . 452
4.7 UART1 Line Control Register (U1LCR -
0xE001 000C). . . . . . . . . . . . . . . . . . . . . . . . 452
4.8 UART1 Modem Control Register (U1MCR -
0xE001 0010) . . . . . . . . . . . . . . . . . . . . . . . . 453
4.9 Auto-flow control . . . . . . . . . . . . . . . . . . . . . . 454
4.9.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
4.10 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
4.11 UART1 Line Status Register (U1LSR -
0xE001 0014, Read Only) . . . . . . . . . . . . . . 456
4.12 UART1 Modem Status Register (U1MSR -
0xE001 0018). . . . . . . . . . . . . . . . . . . . . . . . 457
4.13 UART1 Scratch Pad Register (U1SCR -
0xE001 001C) . . . . . . . . . . . . . . . . . . . . . . . 458
4.14 UART1 Auto-baud Control Register (U1ACR -
0xE001 0020). . . . . . . . . . . . . . . . . . . . . . . . 458
4.15 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 459
4.16 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 460
4.17 UART1 Fractional Divider Register (U1FDR -
0xE001 0028). . . . . . . . . . . . . . . . . . . . . . . . 461
4.17.1 Baudrate calculation . . . . . . . . . . . . . . . . . . 462
4.17.1.1 Example 1: PCLK = 14.7456 MHz,
BR = 9600 . . . . . . . . . . . . . . . . . . . . . . . . . . 464
4.17.1.2 Example 2: PCLK = 12 MHz, BR = 115200 . 464
4.18 UART1 Transmit Enable Register (U1TER -
0xE001 0030). . . . . . . . . . . . . . . . . . . . . . . . 464
5 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Chapter 18: LPC24XX CAN controllers CAN1/2
1 How to read this chapter . . . . . . . . . . . . . . . . 467
2 Basic configuration . . . . . . . . . . . . . . . . . . . . 467
3 CAN controllers . . . . . . . . . . . . . . . . . . . . . . . 467
4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
4.1 General CAN features . . . . . . . . . . . . . . . . . 468
4.2 CAN controller features . . . . . . . . . . . . . . . . 468
4.3 Acceptance filter features . . . . . . . . . . . . . . . 468
5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 468
6 CAN controller architecture . . . . . . . . . . . . . 469
6.1 APB Interface Block (AIB) . . . . . . . . . . . . . . 469
6.2 Interface Management Logic (IML). . . . . . . . 469
6.3 Transmit Buffers (TXB) . . . . . . . . . . . . . . . . . 470
6.4 Receive Buffer (RXB) . . . . . . . . . . . . . . . . . 470
6.5 Error Management Logic (EML) . . . . . . . . . 471
6.6 Bit Timing Logic (BTL) . . . . . . . . . . . . . . . . . 471
6.7 Bit Stream Processor (BSP) . . . . . . . . . . . . . 471
6.8 CAN controller self-tests . . . . . . . . . . . . . . . . 471
Global self test . . . . . . . . . . . . . . . . . . . . . . . .472
Local self test . . . . . . . . . . . . . . . . . . . . . . . . .472
7 Memory map of the CAN block. . . . . . . . . . . 473
8 Register description . . . . . . . . . . . . . . . . . . . 473
8.1 Mode Register (CAN1MOD - 0xE004 4000,
CAN2MOD - 0xE004 8000) . . . . . . . . . . . . . 475
8.2 Command Register (CAN1CMR - 0xE004 x004,
CAN2CMR - 0xE004 8004) . . . . . . . . . . . . . 476
8.3 Global Status Register (CAN1GSR -
0xE004 x008, CAN2GSR - 0xE004 8008) . . 478
RX error counter . . . . . . . . . . . . . . . . . . . . . . .479
TX error counter. . . . . . . . . . . . . . . . . . . . . . . 480
8.4 Interrupt and Capture Register (CAN1ICR -
0xE004 400C, CAN2ICR - 0xE004 800C) . . 480
8.5 Interrupt Enable Register (CAN1IER -
0xE004 4010, CAN2IER - 0xE004 8010). . . 484
8.6 Bus Timing Register (CAN1BTR - 0xE004 4014,
CAN2BTR - 0xE004 8014). . . . . . . . . . . . . . 485
Baud rate prescaler . . . . . . . . . . . . . . . . . . . . 486
Synchronization jump width . . . . . . . . . . . . . . 486
Time segment 1 and time segment 2. . . . . . . 486
8.7 Error Warning Limit Register (CAN1EWL -
0xE004 4018, CAN2EWL - 0xE004 8018). . 487
8.8 Status Register (CAN1SR - 0xE004 401C,
CAN2SR - 0xE004 801C) . . . . . . . . . . . . . . 487
8.9 Receive Frame Status Register (CAN1RFS -
0xE004 4020, CAN2RFS - 0xE004 8020) . . 489
8.9.1 ID index field . . . . . . . . . . . . . . . . . . . . . . . . 490
8.10 Receive Identifier Register (CAN1RID -
0xE004 4024, CAN2RID - 0xE004 8024) . . 490
8.11 Receive Data Register A (CAN1RDA -
0xE004 4028, CAN2RDA - 0xE004 8028) . . 490
8.12 Receive Data Register B (CAN1RDB -
0xE004 402C, CAN2RDB - 0xE004 802C) . 491
8.13 Transmit Frame Information Register
(CAN1TFI[1/2/3] - 0xE004 40[30/ 40/50],
CAN2TFI[1/2/3] - 0xE004 80[30/40/50]) . . . 491
Automatic transmit priority detection . . . . . . . 492
Tx DLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492