NXP Semiconductors LPC24XX UM10237 - Manual (Page 718)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 718 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
5. Programming the GPDMA
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream is
configured to provide unidirectional DMA transfers for a single source and destination.
The source and destination areas can each be either a memory region or a peripheral
which supports the GPDMA, and must be accessible through AHB1.
The following applies to the registers used in the GPDMA:
• Reserved or unused address locations must not be accessed because this can result
in unpredictable behavior of the device.
• Reserved or unused bits of registers must be written as zero, and ignored on read
unless otherwise stated in the relevant text.
• All register bits are reset to a logic 0 by a system or power-on reset unless otherwise
stated in the relevant text.
• Unless otherwise stated in the relevant text, all registers support read and write
accesses. A write updates the contents of a register and a read returns the contents
of the register.
• All registers defined in this document can only be accessed using word reads and
word writes (i.e. 32 bit accesses), unless otherwise stated in the relevant text.
5.1 Enabling the GPDMA
To enable the GPDMA set the DMA Enable bit in the DMACConfiguration Register
(
Section 32–6.1.13 “Configuration Register (DMACConfiguration - 0xFFE0 4030)” .
5.2 Disabling the GPDMA
To disable the GPDMA:
1. Read the DMACEnbldChns Register and ensure that all the DMA channels have
been disabled. If any channels are active, see Section 32–5.4 “Disabling a DMA
channel” .
2. Disable the GPDMA by writing 0 to the DMA Enable bit in the DMACConfiguration
Register ( Section 32–6.2.6 “Channel Configuration Registers (DMACC0Configuration
- 0xFFE0 4110 and DMACC1Configuration - 0xFFE0 4130)” ).
SSP1 Rx 3 3 - -
SD/MMC 4 4 4 4
I 2 S channel 0 - 5 - -
I 2 S channel 1 - 6 - -
Table 651. DMA Connections
Peripheral Function DMA Single
Request Input
DMA Burst
Request Input DMA Last Word
Request Input DMA Last Burst
Request Input