Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
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UM10237_4
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User manual
Rev. 04 — 26 August 2009
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NXP Semiconductors
UM10237
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
, too. Next to providing the same functions as the FIODIR register, these
additional registers allow easier and faster access to the physical port pins.
6.2 GPIO port output Set register IOSET and FIOSET(IO[0/1]SET -
0xE002 80[0/1]4 and FIO[0/1/2/3/4]SET - 0x3FFF C0[1/3/5/7/9]8)
This register is used to produce a HIGH level output at the port pins configured as GPIO in
an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins.
Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing
1 to the corresponding bit in the IOSET has no effect.
Reading the IOSET register returns the value of this register, as determined by previous
writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the
effect of any outside world influence on the I/O pins.
Table 163. Fast GPIO port Direction control byte and half-word accessible register
description
Generic
Register
name
Description
Register
length (bits)
& access
Reset
value
PORTn Register
Address & Name
FIOxDIR0
Fast GPIO Port x Direction
control register 0. Bit 0 in
FIOxDIR0 register corresponds
to pin Px.0 ... bit 7 to pin Px.7.
8 (byte)
R/W
0x00
FIO0DIR0 - 0x3FFF C000
FIO1DIR0 - 0x3FFF C020
FIO2DIR0 - 0x3FFF C040
FIO3DIR0 - 0x3FFF C060
FIO4DIR0 - 0x3FFF C080
FIOxDIR1
Fast GPIO Port x Direction
control register 1. Bit 0 in
FIOxDIR1 register corresponds
to pin Px.8 ... bit 7 to pin Px.15.
8 (byte)
R/W
0x00
FIO0DIR1 - 0x3FFF C001
FIO1DIR1 - 0x3FFF C021
FIO2DIR1 - 0x3FFF C041
FIO3DIR1 - 0x3FFF C061
FIO4DIR1 - 0x3FFF C081
FIO0DIR2
Fast GPIO Port x Direction
control register 2. Bit 0 in
FIOxDIR2 register corresponds
to pin Px.16 ... bit 7 to pin
Px.23.
8 (byte)
R/W
0x00
FIO0DIR2 - 0x3FFF C002
FIO1DIR2 - 0x3FFF C022
FIO2DIR2 - 0x3FFF C042
FIO3DIR2 - 0x3FFF C062
FIO4DIR2 - 0x3FFF C082
FIOxDIR3
Fast GPIO Port x Direction
control register 3. Bit 0 in
FIOxDIR3 register corresponds
to pin Px.24 ... bit 7 to pin
Px.31.
8 (byte)
R/W
0x00
FIO0DIR3 - 0x3FFF C003
FIO1DIR3 - 0x3FFF C023
FIO2DIR3 - 0x3FFF C043
FIO3DIR3 - 0x3FFF C063
FIO4DIR3 - 0x3FFF C083
FIOxDIRL
Fast GPIO Port x Direction
control Lower half-word
register. Bit 0 in FIOxDIRL
register corresponds to pin
Px.0 ... bit 15 to pin Px.15.
16 (half-word)
R/W
0x0000 FIO0DIRL - 0x3FFF C000
FIO1DIRL - 0x3FFF C020
FIO2DIRL - 0x3FFF C040
FIO3DIRL - 0x3FFF C060
FIO4DIRL - 0x3FFF C080
FIOxDIRU
Fast GPIO Port x Direction
control Upper half-word
register. Bit 0 in FIOxDIRU
register corresponds to Px.16
... bit 15 to Px.31.
16 (half-word)
R/W
0x0000 FIO0DIRU - 0x3FFF C002
FIO1DIRU - 0x3FFF C022
FIO2DIRU - 0x3FFF C042
FIO3DIRU - 0x3FFF C062
FIO4DIRU - 0x3FFF C082