NXP Semiconductors LPC24XX UM10237 - Manual (Page 630)

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User manual Rev. 04 — 26 August 2009 630 of 792
NXP Semiconductors
UM10237
Chapter 24: LPC24XX Timer0/1/2/3
7. Example timer operation
Figure 24–129 shows a timer configured to reset the count and generate an interrupt on
match. The prescaler is set to 2 and the match register set to 6. At the end of the timer
cycle where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 24–130 shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
8. Architecture
The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in
Figure 24–131 .
Fig 129. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.
PCLK
prescale
counter
interrupt
timer
counter
timer counter
reset
2 2 2 2 0 0 0 0 1 1 1 1
4 5 6 0 1
Fig 130. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled
PCLK
prescale counter
interrupt
timer counter
TCR[0]
(counter enable)
2 2 0 0 1
4 5 6
1 0