Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual

Page 772

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UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

772 of 792

NXP Semiconductors

UM10237

Chapter 36: LPC24XX Supplementary information

description . . . . . . . . . . . . . . . . . . . . . . . . . . .722

Table 656.Interrupt Error Status register

(DMACIntErrorStatus - address 0xFFE0 400C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .723

Table 657.Interrupt Error Clear register (DMACIntErrClr -

address 0xFFE0 4010) bit description . . . . . .723

Table 658.Raw Interrupt Terminal Count Status register

(DMACRawIntTCStatus - address 0xFFE0 4014)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .723

Table 659.Raw Error Interrupt Status register

(DMACRawIntErrorStatus - address
0xFFE0 4018) bit description . . . . . . . . . . . . .724

Table 660.Enabled Channel register (DMACEnbldChns -

address 0xFFE0 401C) bit description . . . . . .724

Table 661.Software Burst Request register (DMACSoftBReq

- address 0xFFE0 4020) bit description . . . . .724

Table 662.Software Single Request register

(DMACSoftSReq - address 0xFFE0 4024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .725

Table 663.Software Last Burst Request register

(DMACSoftLBReq - address 0xFFE0 4028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .725

Table 664.Software Last Single Request register

(DMACSoftLSReq - address 0xFFE0 402C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .726

Table 665.Configuration register (DMACConfiguration -

address 0xFFE0 4030) bit description . . . . . .726

Table 666.Synchronization register (DMACSync - address

0xFFE0 4034) bit description . . . . . . . . . . . . .726

Table 667.Channel Source Address registers

(DMACC0SrcAddr - address 0xFFE0 4100 and
DMACC1SrcAddr - address 0xFFE0 4120) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .727

Table 668.Channel Destination Address registers

(DMACC0DestAddr - address 0xFFE0 4104 and
DMACC1DestAddr - address 0xFFE0 4124) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .728

Table 669.Channel Linked List Item registers (DMACC0LLI -

address 0xFFE0 4108 and DMACC1LLI - address
0xFFE0 4128) bit description . . . . . . . . . . . . .728

Table 670.Channel Control registers (DMACC0Control -

address 0xFFE0 410C and DMACC1Control -
address 0xFFE0 412C) bit description . . . . . .729

Table 671.Source or destination burst size . . . . . . . . . . .729
Table 672.Source or destination transfer width . . . . . . . .730
Table 673.Protection bits . . . . . . . . . . . . . . . . . . . . . . . . .730
Table 674.Channel Configuration registers

(DMACC0Configuration - address 0xFFE0 4110
and DMACC1Configuration - address
0xFFE0 4130) bit description . . . . . . . . . . . . .731

Table 675.Flow control and transfer type bits . . . . . . . . .733
Table 676.DMA request signal usage . . . . . . . . . . . . . . .737
Table 677.EmbeddedICE pin description . . . . . . . . . . . .741
Table 678.EmbeddedICE logic registers . . . . . . . . . . . . .742
Table 679.ETM configuration . . . . . . . . . . . . . . . . . . . . .744
Table 680.ETM pin description . . . . . . . . . . . . . . . . . . . .745
Table 681.ETM Registers . . . . . . . . . . . . . . . . . . . . . . . .746
Table 682.RealMonitor stack requirement. . . . . . . . . . . .751

Table 683.Acronyms and abbreviations . . . . . . . . . . . . . 759