NXP Semiconductors LPC24XX UM10237 - Manual (Page 562)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 562 of 792
NXP Semiconductors
UM10237
Chapter 21: LPC24XX SD/MMC card interface
• The receive FIFO refers to the receive logic and data buffer when RxActive is
asserted (see
Section 21–5.3.15 “Receive FIFO” ).
5.3.14 Transmit FIFO
Data can be written to the transmit FIFO through the APB interface once the MCI is
enabled for transmission.
The transmit FIFO is accessible via 16 sequential addresses (see Section 21–6.15 “Data
FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)” ). The transmit FIFO contains
a data output register that holds the data word pointed to by the read pointer. When the
data path subunit has loaded its shift register, it increments the read pointer and drives
new data out.
If the transmit FIFO is disabled, all status flags are deasserted. The data path subunit
asserts TxActive when it transmits data.
Table 21–488 lists the transmit FIFO status flags.
5.3.15 Receive FIFO
When the data path subunit receives a word of data, it drives data on the write data bus
and asserts the write enable signal. This signal is synchronized to the PCLK domain. The
write pointer is incremented after the write is completed, and the receive FIFO control
logic asserts RxWrDone, that then deasserts the write enable signal.
On the read side, the content of the FIFO word pointed to by the current value of the read
pointer is driven on the read data bus. The read pointer is incremented when the APB bus
interface asserts RxRdPrtInc.
If the receive FIFO is disabled, all status flags are deasserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data. Table
353 lists the receive FIFO status flags.
The receive FIFO is accessible via 16 sequential addresses (see Section 21–6.15 “Data
FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)” ).
If the receive FIFO is disabled, all status flags are deasserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data.
Table 21–489 lists the receive FIFO status flags.
Table 488. Transmit FIFO status flags
Flag Description
TxFifoFull Set to HIGH when all 16 transmit FIFO words contain valid data.
TxFifoEmpty Set to HIGH when the transmit FIFO does not contain valid data.
TxHalfEmpty Set to HIGH when 8 or more transmit FIFO words are empty. This flag
can be used as a DMA request.
TxDataAvlbl Set to HIGH when the transmit FIFO contains valid data. This flag is the
inverse of the TxFifoEmpty flag.
TxUnderrun Set to HIGH when an underrun error occurs. This flag is cleared by
writing to the MCIClear register.