NXP Semiconductors LPC24XX UM10237 - Manual (Page 423)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 423 of 792
1. Basic configuration
The UART0/2/3 peripherals are configured using the following registers:
1. Power: In the PCONP register ( Table 4–63 ), set bits PCUART0/2/3.
Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled
(PCUART2/3 = 0).
2. Peripheral clock: In the PCLK_SEL0 register ( Table 4–56 ), select PCLK_UART0; in
the PCLK_SEL1 register ( Table 4–57 ), select PCLK_UART2/3.
3. Baud rate: In register U0/2/3LCR ( Table 16–386 ), set bit DLAB =1. This enables
access to registers DLL ( Table 16–380 ) and DLM ( Table 16–381 ) for setting the baud
rate. Also, if needed, set the fractional baud rate in the fractional divider register
(
Table 16–392 ).
4. UART FIFO: Use bit FIFO enable (bit 0) in register U0/2/3FCR ( Table 16–385 ) to
enable FIFO.
5. Pins: Select UART pins and pin modes in registers PINSELn and PINMODEn (see
Section 9–5 ).
Remark: UART receive pins should not have pull-down resistors enabled.
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U0/2/3LCR
( Table 16–386 ). This enables access to U0/2/3IER ( Table 16–382 ). Interrupts are
enabled in the VIC using the VICIntEnable register ( Table 7–106 ).
2. Features
• 16 byte Receive and Transmit FIFOs.
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
• Built-in baud rate generator.
• Fractional divider for baud rate control and mechanism that enables software flow
control implementation.
• In addition, UART3 includes an IrDA mode to support infrared communication.
3. Pin description
UM10237
Chapter 16: LPC24XX UART0/2/3
Rev. 04 — 26 August 2009 User manual
Table 376. UART0 Pin description
Pin Type Description
RXD0, RXD2, RXD3 Input Serial Input. Serial receive data.
TXD0, TXD2, TXD3 Output Serial Output. Serial transmit data.