NXP Semiconductors LPC24XX UM10237 - Manual (Page 582)

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User manual Rev. 04 — 26 August 2009 582 of 792
NXP Semiconductors
UM10237
Chapter 22: LPC24XX I 2 C interfaces I 2 C0/1/2
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
8.1 I 2 C Control Set Register (I2C[0/1/2]CONSET: 0xE001 C000,
0xE005 C000, 0xE008 0000)
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I
2 C interface. Writing a one to a bit of this register causes the
corresponding bit in the I 2 C control register to be set. Writing a zero has no effect.
I2EN I 2 C Interface Enable. When I2EN is 1, the I 2 C interface is enabled. I2EN can be
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I 2 C
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I 2 C block is in the “not
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I 2 C bus since, when I2EN is reset, the
I 2 C bus status is lost. The AA flag should be used instead.
STA is the START flag. Setting this bit causes the I 2 C interface to enter master mode and
transmit a START condition or transmit a repeated START condition if it is already in
master mode.
I2SCLH SCH Duty Cycle Register High Half Word.
Determines the high time of the I 2 C clock.
R/W 0x04 I2C0SCLH - 0xE001 C010
I2C1SCLH - 0xE005 C010
I2C2SCLH - 0xE008 0010
I2SCLL SCL Duty Cycle Register Low Half Word.
Determines the low time of the I 2 C clock. I2nSCLL
and I2nSCLH together determine the clock frequency
generated by an I
2 C master and certain times used in
slave mode.
R/W 0x04 I2C0SCLL - 0xE001 C014
I2C1SCLL - 0xE005 C014
I2C2SCLL - 0xE008 0014
I2CONCLR I2C Control Clear Register. When a one is written to
a bit of this register, the corresponding bit in the I 2 C
control register is cleared. Writing a zero has no effect
on the corresponding bit in the I
2 C control register.
WO NA I2C0CONCLR - 0xE001 C018
I2C1CONCLR - 0xE005 C018
I2C2CONCLR - 0xE008 0018
Table 512. Summary of I 2 C registers
Generic
Name Description Access Reset
value
[1]
I 2 Cn Register
Name & Address
Table 513. I 2 C Control Set Register (I2C[0/1/2]CONSET - addresses: 0xE001 C000,
0xE005 C000, 0xE008 0000) bit description
Bit Symbol Description Reset
Value
1:0 - Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
2 AA Assert acknowledge flag. See the text below.
3 SI I 2 C interrupt flag. 0
4 STO STOP flag. See the text below. 0
5 STA START flag. See the text below. 0
6 I2EN I 2 C interface enable. See the text below. 0
7 - Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA