NXP Semiconductors LPC24XX UM10237 - Manual (Page 345)

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User manual Rev. 04 — 26 August 2009 345 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
9.4.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0xFFE0 C238)
Writing a one to this a bit in this register causes the SIE Select Endpoint/Clear Interrupt
command to be executed (
Table 13–354 ) for the corresponding physical endpoint. Writing
zero has no effect. Before executing the Select Endpoint/Clear Interrupt command, the
CDFULL bit in USBDevIntSt is cleared by hardware. On completion of the command, the
CDFULL bit is set, USBCmdData contains the status of the endpoint, and the
corresponding bit in USBEpIntSt is cleared.
Notes:
• When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be
set to ensure the corresponding interrupt has been cleared before proceeding.
• While setting multiple bits in USBEpIntClr simultaneously is possible, it is not
recommended; only the status of the endpoint corresponding to the least significant
interrupt bit cleared will be available at the end of the operation.
• Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly
invoked using the SIE command registers, but using USBEpIntClr is recommended
because of its ease of use.
Each physical endpoint has its own reserved bit in this register. The bit field definition is
the same as that of USBEpIntSt shown in
Table 13–307 . USBEpIntClr is a write only
register.
Table 309. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xFFE0 C234) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX
Table 310. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xFFE0 C234) bit description
Bit Symbol Value Description Reset value
31:0 See
USBEpIntEn
bit allocation
table above 0 The corresponding bit in USBDMARSt is set when an interrupt occurs for
this endpoint. 0
1 The corresponding bit in USBEpIntSt is set when an interrupt occurs
for this endpoint.
Implies Slave mode for this endpoint.
Table 311. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xFFE0 C238) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX