NXP Semiconductors LPC24XX UM10237 - Manual (Page 74)

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User manual Rev. 04 — 26 August 2009 74 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
8. Reset
The EMC receives two reset signals. One is Power-On Reset (POR), asserted when chip
power is applied, and when a brown-out condition is detected (see the System Control
Block chapter for details of Brown-Out Detect). The other reset is from the external Reset
pin and the Watchdog Timer.
A configuration bit in the SCS register, called EMC_Reset_Disable, allows control of how
the EMC is reset. The default configuration (EMC_Reset_Disable = 0) is that both EMC
resets are asserted when any type of reset event occurs. In this mode, all registers and
functions of the EMC are initialized upon any reset condition.
If EMC_Reset_Disable is set to 1, many portions of the EMC are only reset by a power-on
or brown-out event, in order to allow the EMC to retain its state through a warm reset
(external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be
maintained through a warm reset.
9. Pin description
Table 5–66 shows the interface and control signal pins for the EMC.
Table 66. Pad interface and control signal descriptions
Name Type Value on POR
reset Value during
self-refresh Description
A[23:0] Output 0x0000 0000 Depends on
static memory
accesses External memory address output.
Used for both static and SDRAM
devices. SDRAM memories use only
bits [14:0].
D[31:0] Input/
Output Data outputs =
0x0000 0000 Depends on
static memory
accesses External memory data lines. These
are inputs when data is read from
external memory and outputs when
data is written to external memory.
OE Output 1 Depends on
static memory
accesses Low active output enable for static
memory devices.
BLS[3:0] Output 0xF Depends on
static memory
accesses Low active byte lane selects. Used
for static memory devices.
WE Output 1 Depends on
static memory
accesses Low active write enable. Used for
SDRAM and static memories.
CS[3:0] Output 0xF Depends on
static memory
accesses Static memory chip selects. Default
active LOW. Used for static memory
devices.
DYCS[3:0] Output 0xF 0xF SDRAM chip selects. Used for
SDRAM devices.
CAS Output 1 1 Column address strobe. Used for
SDRAM devices.
RAS Output 1 1 Row address strobe. Used for
SDRAM devices.