NXP Semiconductors LPC24XX UM10237 - Manual (Page 724)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 724 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
6.1.8 Enabled Channel Register (DMACEnbldChns - 0xFFE0 401C)
The DMACEnbldChns Register is read-only and indicates which DMA channels are
enabled, as indicated by the Enable bit in the DMACCxConfiguration Register. A HIGH bit
indicates that a DMA channel is enabled. A bit is cleared on completion of the DMA
transfer.
Table 32–660 shows the bit assignments of the DMACEnbldChns Register.
6.1.9 Software Burst Request Register (DMACSoftBReq - 0xFFE0 4020)
The DMACSoftBReq Register is read/write and enables DMA burst requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Writing 0 to this register has no effect. Reading the register indicates which
sources are requesting DMA burst transfers. A request can be generated from either a
peripheral or the software request register.
Table 32–661 shows the bit assignments of the
DMACSoftBReq Register.
Note: It is recommended that software and hardware peripheral requests are not used at
the same time.
Table 659. Raw Error Interrupt Status register (DMACRawIntErrorStatus - address
0xFFE0 4018) bit description
Bit Symbol Description Reset
Value
0 RawIntErrorStatus0 Status of the error interrupt for channel 0 prior to masking. -
1 RawIntErrorStatus1 Status of the error interrupt for channel 1 prior to masking. -
31:2 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 660. Enabled Channel register (DMACEnbldChns - address 0xFFE0 401C) bit
description
Bit Symbol Description Reset
Value
0 EnabledChannels0 Enable status for Channel 0. 0
1 EnabledChannels1 Enable status for Channel 1. 0
31:2 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 661. Software Burst Request register (DMACSoftBReq - address 0xFFE0 4020) bit
description
Bit Symbol Description Reset
Value
0 SoftBReqSSP0Tx Software burst request flag for SSP0 Tx. 0
1 SoftBReqSSP0Rx Software burst request flag for SSP0 Rx. 0
2 SoftBReqSSP1Tx Software burst request flag for SSP1 Tx. 0
3 SoftBReqSSP1Rx Software burst request flag for SSP1 Rx. 0
4 SoftBReqSDMMC Software burst request flag for SD/MMC. 0
5 SoftBReqI2S0 Software burst request flag for I 2 S0. 0
6 SoftBReqI2S1 Software burst request flag for I 2 S1. 0
31:7 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA