NXP Semiconductors LPC24XX UM10237 - Manual (Page 545)

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User manual Rev. 04 — 26 August 2009 545 of 792
NXP Semiconductors
UM10237
Chapter 20: LPC24XX SSP interface SSP0/1
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
6.1 SSPn Control Register 0 (SSP0CR0 - 0xE006 8000, SSP1CR0 - 0xE003
0000)
This register controls the basic operation of the SSP controller.
Table 470. SSP Register Map
Generic Name Description Access Reset
Value
[1]
SSPn Register
Name & Address
CR0 Control Register 0. Selects the serial clock rate, bus
type, and data size. R/W 0 SSP0CR0 - 0xE006 8000
SSP1CR0 - 0xE003 0000
CR1 Control Register 1. Selects master/slave and other
modes. R/W 0 SSP0CR1 - 0xE006 8004
SSP1CR1 - 0xE003 0004
DR Data Register. Writes fill the transmit FIFO, and
reads empty the receive FIFO. R/W 0 SSP0DR - 0xE006 8008
SSP1DR - 0xE003 0008
SR Status Register RO SSP0SR - 0xE006 800C
SSP1SR - 0xE003 000C
CPSR Clock Prescale Register R/W 0 SSP0CPSR - 0xE006 8010
SSP1CPSR - 0xE003 0010
IMSC Interrupt Mask Set and Clear Register R/W 0 SSP0IMSC - 0xE006 8014
SSP1IMSC - 0xE003 0014
RIS Raw Interrupt Status Register R/W SSP0RIS - 0xE006 8018
SSP1RIS - 0xE003 0018
MIS Masked Interrupt Status Register R/W 0 SSP0MIS - 0xE006 801C
SSP1MIS - 0xE003 001C
ICR SSPICR Interrupt Clear Register R/W NA SSP0ICR - 0xE006 8020
SSP1ICR - 0xE003 0020
DMACR DMA Control Register R/W 0 SSP0DMACR - 0xE006 8024
SSP1DMACR - 0xE003 0024