Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
Page 762
UM10237_4
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 04 — 26 August 2009
762 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
0xFFE0 8028) bit description . . . . . . . . . . . . . .82
Table 74. Dynamic Memory Percentage Command Period
register (EMCDynamictRP - address
0xFFE0 8030) bit description . . . . . . . . . . . . . .83
Table 75. Dynamic Memory Active to Precharge Command
Period register (EMCDynamictRAS - address
0xFFE0 8034) bit description . . . . . . . . . . . . . .83
Table 76. Dynamic Memory Self-refresh Exit Time register
Table 77. Memory Last Data Out to Active Time register
Table 78. Dynamic Memory Data-in to Active Command
Time register (EMCDynamictDAL - address
0xFFE0 8040) bit description . . . . . . . . . . . . . .85
Table 79. Dynamic Memory Write recover Time register
Table 80. Dynamic Mempry Active to Active Command
Period register (EMCDynamictRC - address
0xFFE0 8048) bit description . . . . . . . . . . . . . .86
Table 81. Dynamic Memory Auto-refresh Period register
Table 82. Dynamic Memory Exit Self-refresh register
Table 83. Dynamic Memory Acitve Bank A to Active Bank B
Time register (EMCDynamictRRD - address
0xFFE0 8054) bit description . . . . . . . . . . . . . .87
Table 84. Dynamic Memory Load Mode register to Active
Command Time (EMCDynamictMRD - address
0xFFE0 8058) bit description . . . . . . . . . . . . . .88
Table 85. Static Memory Extended Wait register
(EMCStaticExtendedWait - address
0xFFE0 8080) bit description . . . . . . . . . . . . . .88
Table 86. Dynamic Memory Configuration registers
Table 87. Address mapping . . . . . . . . . . . . . . . . . . . . . . .89
Table 88. Dynamic Memory RAS & CAS Delay registers
Table 89. Static Memory Configuration registers
Table 90. Static Memory Write Enable Delay registers
Table 91. Static Memory Output Enable delay registers
Table 92. Static Memory Read Delay registers
Table 93. Static Memory Page Mode Read Delay
Table 94. Static Memory Write Delay registers0-3
Table 95. Static Memory Trun Round Delay registers0-3
Table 96. MAM responses to program accesses of various
types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 97. MAM responses to data and DMA accesses of
various types . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 98. Summary of Memory Acceleration Module
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 99. MAM Control Register (MAMCR - address
0xE01F C000) bit description. . . . . . . . . . . . . 105
Table 100.MAM Timing register (MAMTIM - address
0xE01F C004) bit description. . . . . . . . . . . . . 106
Table 101.Suggestions for MAM timing selection. . . . . . 108
Table 102.Summary of VIC registers . . . . . . . . . . . . . . . 110
Table 103.Software Interrupt register (VICSoftInt - address
0xFFFF F018) bit description. . . . . . . . . . . . . 112
Table 104.Software Interrupt Clear register (VICSoftIntClear
- address 0xFFFF F01C) bit description . . . . 112
Table 105.Raw Interrupt Status register (VICRawIntr -
address 0xFFFF F008) bit description . . . . . . 113
Table 106.Interrupt Enable register (VICIntEnable - address
0xFFFF F010) bit description. . . . . . . . . . . . . 113
Table 107.Interrupt Enable Clear register (VICIntEnClear -
address 0xFFFF F014) bit description . . . . . . 113
Table 108.Interrupt Select register (VICIntSelect - address
0xFFFF F00C) bit description . . . . . . . . . . . . 114
Table 109.IRQ Status register (VICIRQStatus - address
0xFFFF F000) bit description. . . . . . . . . . . . . 114
Table 110. FIQ Status register (VICFIQStatus - address
0xFFFF F004) bit description. . . . . . . . . . . . . 114
Table 111. Vector Address registers 0-31 (VICVectAddr0-31 -
Table 112. Vector Priority registers 0-31 (VICVectPriority0-31
Table 113. Vector Address register (VICAddress - address
0xFFFF FF00) bit description. . . . . . . . . . . . . 115
Table 114. Software Priority Mask register
Table 115. Protection Enable register (VICProtection -