NXP Semiconductors LPC24XX UM10237 - Manual (Page 776)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 776 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
3.2.12 Procedure for determining PLL settings . . . . . 54
3.2.13 Examples of PLL settings . . . . . . . . . . . . . . . . 55
3.2.14 PLL setup sequence . . . . . . . . . . . . . . . . . . . . 56
3.3 Clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.1 CPU Clock Configuration register (CCLKCFG -
0xE01F C104) . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.2 USB Clock Configuration register (USBCLKCFG -
0xE01F C108) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.3 IRC Trim Register (IRCTRIM - 0xE01F C1A4) 58
3.3.4 Peripheral Clock Selection registers 0 and 1
(PCLKSEL0 - 0xE01F C1A8 and PCLKSEL1 -
0xE01F C1AC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.4 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 61
3.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 61
3.4.5 Peripheral power control . . . . . . . . . . . . . . . . 62
3.4.6 Power control register description . . . . . . . . . 62
3.4.7 Power Mode Control register (PCON -
0xE01F C0C0) . . . . . . . . . . . . . . . . . . . . . . . . 62
Encoding of reduced power modes . . . . . . . . . 63
3.4.8 Interrupt Wakeup Register (INTWAKE -
0xE01F C144) . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.9 Power Control for Peripherals register (PCONP -
0xE01F C0C4) . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4.10 Power control usage notes . . . . . . . . . . . . . . 66
4 Power domains . . . . . . . . . . . . . . . . . . . . . . . . 66
5 Wakeup timer. . . . . . . . . . . . . . . . . . . . . . . . . . 67
Chapter 5: LPC24XX External Memory Controller (EMC)
1 How to read this chapter . . . . . . . . . . . . . . . . . 68
2 Basic configuration . . . . . . . . . . . . . . . . . . . . . 68
3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5 EMC functional description . . . . . . . . . . . . . . 69
5.1 AHB slave register interface . . . . . . . . . . . . . . 70
5.2 AHB slave memory interface . . . . . . . . . . . . . 71
5.2.1 Memory transaction endianness. . . . . . . . . . . 71
5.2.2 Memory transaction size. . . . . . . . . . . . . . . . . 71
5.2.3 Write protected memory areas . . . . . . . . . . . . 71
5.3 Pad interface . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4 Data buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.1 Write buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.2 Read buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5 Memory controller state machine . . . . . . . . . . 72
6 Low-power operation. . . . . . . . . . . . . . . . . . . . 72
6.1 Low-power SDRAM Deep-sleep Mode. . . . . . 73
6.2 Low-power SDRAM partial array refresh . . . . 73
7 Memory bank select . . . . . . . . . . . . . . . . . . . . 73
8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 74
10 Register description . . . . . . . . . . . . . . . . . . . . 75
10.1 EMC Control register (EMCControl -
0xFFE0 8000) . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.2 EMC Status register (EMCStatus -
0xFFE0 8004) . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3 EMC Configuration register (EMCConfig -
0xFFE0 8008) . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4 Dynamic Memory Control register
(EMCDynamicControl - 0xFFE0 8020) . . . . . . 79
10.5 Dynamic Memory Refresh Timer register
(EMCDynamicRefresh - 0xFFE0 8024) . . . . . 81
10.6 Dynamic Memory Read Configuration register
(EMCDynamicReadConfig - 0xFFE0 8028) . . 82
10.7 Dynamic Memory Percentage Command Period
register (EMCDynamictRP - 0xFFE0 8030) . . 82
10.8 Dynamic Memory Active to Precharge Command
Period register (EMCDynamictRAS -
0xFFE0 8034) . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.9 Dynamic Memory Self-refresh Exit Time register
(EMCDynamictSREX - 0xFFE0 8038) . . . . . . 83
10.10 Dynamic Memory Last Data Out to Active Time
register (EMCDynamictAPR - 0xFFE0 803C) 84
10.11 Dynamic Memory Data-in to Active Command
Time register (EMCDynamictDAL -
0xFFE0 8040) . . . . . . . . . . . . . . . . . . . . . . . . 84
10.12 Dynamic Memory Write Recovery Time register
(EMCDynamictWR - 0xFFE0 8044) . . . . . . . . 85
10.13 Dynamic Memory Active to Active Command
Period register (EMCDynamictRC -
0xFFE0 8048) . . . . . . . . . . . . . . . . . . . . . . . . 85
10.14 Dynamic Memory Auto-refresh Period register
(EMCDynamictRFC - 0xFFE0 804C) . . . . . . . 86
10.15 Dynamic Memory Exit Self-refresh register
(EMCDynamictXSR - 0xFFE0 8050) . . . . . . . 86
10.16 Dynamic Memory Active Bank A to Active Bank B
Time register (EMCDynamictRRD -
0xFFE0 8054) . . . . . . . . . . . . . . . . . . . . . . . . 87
10.17 Dynamic Memory Load Mode register to Active
Command Time (EMCDynamictMRD -
0xFFE0 8058) . . . . . . . . . . . . . . . . . . . . . . . . 87
10.18 Static Memory Extended Wait register
(EMCStaticExtendedWait - 0xFFE0 8080). . . 88
10.19 Dynamic Memory Configuration registers
(EMCDynamicConfig0-3 - 0xFFE0 8100, 120,
140, 160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.20 Dynamic Memory RAS & CAS Delay registers
(EMCDynamicRASCAS0-3 - 0xFFE0 8104, 124,
144, 164) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.21 Static Memory Configuration registers
(EMCStaticConfig0-3 - 0xFFE0 8200, 220, 240,
260) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.22 Static Memory Write Enable Delay registers
(EMCStaticWaitWen0-3 - 0xFFE0 8204, 224, 244
,264). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.23 Static Memory Output Enable Delay registers
(EMCStaticWaitOen0-3 - 0xFFE0 8208, 228, 248,
268) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94