NXP Semiconductors LPC24XX UM10237 - Manual (Page 791)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 791 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
4.2.8 Endian behavior . . . . . . . . . . . . . . . . . . . . . . 714
4.2.9 Error conditions . . . . . . . . . . . . . . . . . . . . . . 716
4.2.10 Channel hardware . . . . . . . . . . . . . . . . . . . . 717
4.2.11 DMA request priority . . . . . . . . . . . . . . . . . . . 717
4.2.12 Interrupt generation . . . . . . . . . . . . . . . . . . . 717
4.2.13 The completion of the DMA transfer
indication . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
4.3 DMA system connections . . . . . . . . . . . . . . . 717
5 Programming the GPDMA. . . . . . . . . . . . . . . 718
5.1 Enabling the GPDMA . . . . . . . . . . . . . . . . . . 718
5.2 Disabling the GPDMA. . . . . . . . . . . . . . . . . . 718
5.3 Enabling a DMA channel . . . . . . . . . . . . . . . 719
5.4 Disabling a DMA channel . . . . . . . . . . . . . . . 719
5.5 Disabling a DMA channel without losing data in
the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
5.6 Setup a new DMA transfer . . . . . . . . . . . . . . 719
5.7 Disabling a DMA channel and losing data in the
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
5.8 Halting a DMA transfer . . . . . . . . . . . . . . . . . 719
5.9 Programming a DMA channel. . . . . . . . . . . . 720
6 Register description . . . . . . . . . . . . . . . . . . . 720
6.1 General GPDMA registers . . . . . . . . . . . . . . 721
6.1.1 Interrupt Status Register (DMACIntStatus -
0xFFE0 4000) . . . . . . . . . . . . . . . . . . . . . . . . 721
6.1.2 Interrupt Terminal Count Status Register
(DMACIntTCStatus - 0xFFE0 4004) . . . . . . . 722
6.1.3 Interrupt Terminal Count Clear Register
(DMACIntClear - 0xFFE0 4008) . . . . . . . . . . 722
6.1.4 Interrupt Error Status Register
(DMACIntErrorStatus - 0xFFE0 400C) . . . . . 722
6.1.5 Interrupt Error Clear Register (DMACIntErrClr -
0xFFE0 4010) . . . . . . . . . . . . . . . . . . . . . . . . 723
6.1.6 Raw Interrupt Terminal Count Status Register
(DMACRawIntTCStatus - 0xFFE0 4014) . . . 723
6.1.7 Raw Error Interrupt Status Register
(DMACRawIntErrorStatus - 0xFFE0 4018). . 723
6.1.8 Enabled Channel Register (DMACEnbldChns -
0xFFE0 401C) . . . . . . . . . . . . . . . . . . . . . . . 724
6.1.9 Software Burst Request Register
(DMACSoftBReq - 0xFFE0 4020). . . . . . . . . 724
6.1.10 Software Single Request Register
(DMACSoftSReq - 0xFFE0 4024). . . . . . . . . 725
6.1.11 Software Last Burst Request Register
(DMACSoftLBreq - 0xFFE0 4028) . . . . . . . . 725
6.1.12 Software Last Single Request Register
(DMACSoftLSReq - 0xFFE0 402C) . . . . . . . 725
6.1.13 Configuration Register (DMACConfiguration -
0xFFE0 4030) . . . . . . . . . . . . . . . . . . . . . . . 726
6.1.14 Synchronization Register (DMACSync -
0xFFE0 4034) . . . . . . . . . . . . . . . . . . . . . . . 726
6.2 Channel registers. . . . . . . . . . . . . . . . . . . . . 727
6.2.1 Channel Source Address Registers
(DMACC0SrcAddr - 0xFFE0 4100 and
DMACC1SrcAddr - 0xFFE0 4120). . . . . . . . 727
6.2.2 Channel Destination Address Registers
(DMACC0DestAddr - 0xFFE0 4104 and
DMACC1DestAddr - 0xFFE0 4124). . . . . . . 727
6.2.3 Channel Linked List Item Registers (DMACC0LLI
- 0xFFE0 4108 and DMACC1LLI -
0xFFE0 4128) . . . . . . . . . . . . . . . . . . . . . . . 728
6.2.4 Channel Control Registers (DMACC0Control -
0xFFE0 410C and DMACC0Control -
0xFFE0 412C) . . . . . . . . . . . . . . . . . . . . . . . 728
6.2.5 Protection and Access Information . . . . . . . 730
6.2.6 Channel Configuration Registers
(DMACC0Configuration - 0xFFE0 4110 and
DMACC1Configuration - 0xFFE0 4130) . . . 731
6.2.7 Lock control . . . . . . . . . . . . . . . . . . . . . . . . . 732
6.2.8 Flow control and transfer type . . . . . . . . . . . 733
7 Address generation . . . . . . . . . . . . . . . . . . . 733
8 Scatter/Gather . . . . . . . . . . . . . . . . . . . . . . . . 733
8.1 Linked List Items . . . . . . . . . . . . . . . . . . . . . 733
8.2 Programming the GPDMA for scatter/gather DMA
734
8.3 Example of scatter/gather DMA . . . . . . . . . . 734
9 Interrupt requests . . . . . . . . . . . . . . . . . . . . . 735
9.1 Hardware interrupt sequence flow . . . . . . . . 736
9.2 Interrupt polling sequence flow . . . . . . . . . . 736
10 GPDMA data flow . . . . . . . . . . . . . . . . . . . . . 736
10.1 Peripheral-to-memory, or Memory-to-peripheral
DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
10.2 Peripheral-to-peripheral DMA flow. . . . . . . . 737
10.3 Memory-to-memory DMA flow . . . . . . . . . . . 738
11 Flow control. . . . . . . . . . . . . . . . . . . . . . . . . . 739
Chapter 33: LPC24XX EmbeddedICE
1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 740
3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 741
5 JTAG function select. . . . . . . . . . . . . . . . . . . 742
6 Register description . . . . . . . . . . . . . . . . . . . 742
7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 742
Chapter 34: LPC24XX Embedded Trace Module (ETM)
1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 744
3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
3.1 ETM configuration . . . . . . . . . . . . . . . . . . . . 744
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 745
5 Register description . . . . . . . . . . . . . . . . . . . 745
6 Reset state of multiplexed pins . . . . . . . . . . 746
7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 747