NXP Semiconductors LPC24XX UM10237 - Manual (Page 546)

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User manual Rev. 04 — 26 August 2009 546 of 792
NXP Semiconductors
UM10237
Chapter 20: LPC24XX SSP interface SSP0/1
6.2 SSPn Control Register 1 (SSP0CR1 - 0xE006 8004, SSP1CR1 -
0xE003 0004)
This register controls certain aspects of the operation of the SSP controller.
Table 471: SSPn Control Register 0 (SSP0CR0 - address 0xE006 8000, SSP1CR0 -
0xE003 0000) bit description
Bit Symbol Value Description Reset
Value
3:0 DSS Data Size Select. This field controls the number of bits
transferred in each frame. Values 0000-0010 are not
supported and should not be used. 0000
0011 4 bit transfer
0100 5 bit transfer
0101 6 bit transfer
0110 7 bit transfer
0111 8 bit transfer
1000 9 bit transfer
1001 10 bit transfer
1010 11 bit transfer
1011 12 bit transfer
1100 13 bit transfer
1101 14 bit transfer
1110 15 bit transfer
1111 16 bit transfer
5:4 FRF Frame Format. 00
00 SPI
01 TI
10 Microwire
11 This combination is not supported and should not be used.
6 CPOL Clock Out Polarity. This bit is only used in SPI mode. 0
0 SSP controller maintains the bus clock low between frames.
1 SSP controller maintains the bus clock high between frames.
7 CPHA Clock Out Phase. This bit is only used in SPI mode. 0
0 SSP controller captures serial data on the first clock transition
of the frame, that is, the transition away from the inter-frame
state of the clock line.
1 SSP controller captures serial data on the second clock
transition of the frame, that is, the transition back to the
inter-frame state of the clock line.
15:8 SCR Serial Clock Rate. The number of prescaler-output clocks per
bit on the bus, minus one. Given that CPSDVSR is the
prescale divider, and the APB clock PCLK clocks the
prescaler, the bit frequency is PCLK / (CPSDVSR
× [SCR+1]).
0x00