NXP Semiconductors LPC24XX UM10237 - Manual (Page 389)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 389 of 792
1. Basic configuration
The USB controller is configured using the following registers:
1. Power: In the PCONP register ( Table 4–63 ), set bit PCUSB.
Remark: On reset, the USB block is disabled (PCUSB = 0).
2. Clock: see Table 4–54 .
3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to
PINMODE5 ( Section 9–5 ).
4. Wakeup: Use the INTWAKE register ( Table 4–62 ) to enable activity on the USB bus
port to wakeup the microcontroller from Power-down mode.
5. Interrupts: Interrupts are enabled in the VIC using the VICIntEnable register
( Table 7–106 ).
6. Initialization: see Section 15–10 .
2. Introduction
This section describes the host portion of the USB 2.0 OTG dual role core which
integrates the host controller (OHCI compliant), device controller and I2C. The I2C
interface controls the external OTG ATX.
The USB is a 4 wire bus that supports communication between a host and a number (127
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.
2.1 Features
• OHCI compliant.
UM10237
Chapter 14: LPC24XX USB Host controller
Rev. 04 — 26 August 2009 User manual
Table 358. USB (OHCI) related acronyms and abbreviations used in this chapter
Acronym/abbreviation Description
AHB Advanced High-Performance Bus
ATX Analog Transceiver
DMA Direct Memory Access
FS Full Speed
LS Low Speed
OHCI Open Host Controller Interface
USB Universal Serial Bus